Devices with multiple threshold voltages formed on a single wafer using strain in the high-K layer

Patent metadata

Field	Value
Publication number	US-9627484-B1
Application number	US-201514880918-A
Country	US
Kind code	B1
Filing date	Oct 12, 2015
Priority date	Oct 12, 2015
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.

First claim

The invention claimed is:

1. A method for adjusting a threshold voltage, comprising:
depositing a strained liner on a gate structure to strain a gate dielectric;
adjusting threshold voltage of a transistor after the strained liner is deposited by controlling an amount of strain in the strained liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region; and
removing the strained liner.

2. The method as recited in claim 1 , wherein depositing the strained liner includes depositing a silicon nitride liner and controlling the strain by one or more of: deposition temperature or liner thickness.

3. The method as recited in claim 1 , wherein the gate dielectric includes a high-k dielectric in which a diffusion length of the WF modulating species is modulated in accordance with the strained liner.

4. The method as recited in claim 1 , wherein the WF modulating species are present in the strained liner and further comprising diffusing the WF modulating species by annealing the strained liner.

5. The method as recited in claim 1 , further comprising implanting the WF modulating species through the strained liner to diffuse the WF modulating species into the gate dielectric.

6. The method as recited in claim 1 , wherein the WF modulating species include O and/or OH.

7. The method as recited in claim 1 , wherein adjusting threshold voltage of the transistor includes adjusting threshold voltages of a plurality of transistors using more than one strained liner such that more than one threshold voltage is programmed across a same device.

8. The method as recited in claim 7 , wherein the more than one strained liner, each includes different strain levels to provide different threshold voltages.

9. A method for adjusting threshold voltage, comprising:
depositing two or more liners on two or more different regions of a device, such that the liners impart two or more different strain levels on respective gate dielectric layers;
introducing work function (WF) modulating species to the gate dielectric layers wherein due to the different strain levels in the gate dielectric layers, different amounts of the WF modulating species diffuse to the gate dielectric layers at a channel region, resulting in different threshold voltage values; and
removing the two or more liners.

10. The method as recited in claim 9 , wherein depositing includes depositing two or more silicon nitride liners and controlling the strain by one or more of: deposition temperature or liner thickness.

11. The method as recited in claim 9 , wherein the gate dielectric includes a high-k dielectric in which the diffusion length of the WF modulating species is modulated in accordance with strain in the two or more liners.

12. The method as recited in claim 9 , wherein the WF modulating species are present in the two or more liners and further comprising diffusing the WF modulating species by annealing the two or more liners.

13. The method as recited in claim 9 , further comprising implanting the WF modulating species through the two or more liners to diffuse the WF modulating species into the gate dielectric layers.

14. The method as recited in claim 9 , wherein the WF modulating species include O and/or OH.

15. The method as recited in claim 9 , wherein the two or more liners are employed to adjust threshold voltages across a same device wherein the device includes a chip.

Assignees

• IBM

Inventors

• Ando Takashi
• Bajaj Mohit
• Hook Terence B
• Pandey Rajan K
• Sathiyanarayanan Rajesh

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/20

  Diffusion for doping of insulating layers · CPC title

• H10P32/14

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title

• H10P30/40

  into insulating materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title