Method of making a three-dimensional memory array with etch stop

Patent metadata

Field	Value
Publication number	US-9437606-B2
Application number	US-201313933236-A
Country	US
Kind code	B2
Filing date	Jul 2, 2013
Priority date	Jul 2, 2013
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A method of making a semiconductor device including forming a sacrificial feature over a substrate, forming a plurality of etch through regions having an etch through material and an etch stop region having an etch stop material over the sacrificial feature, forming a stack of alternating layers of a first material and a second material over the plurality of the etch through regions and the plurality of the etch stop regions, etching the stack to form a plurality of openings through the stack and through the etch through regions to expose the sacrificial feature, such that the etch through material is etched preferentially compared to the first and the second materials of the stack, removing the sacrificial feature through the plurality of openings and etching the stack to form a slit trench up to or only partially through the etch stop region, such that the first and the second materials of the stack are etched preferentially compared to the etch stop material.

First claim

What is claimed is:

1. A method of making a semiconductor device, comprising:
forming a sacrificial feature over a substrate;
forming a plurality of etch through regions comprising an etch through material and an etch stop region comprising an etch stop material over the sacrificial feature;
forming a stack of alternating layers of a first material and a second material over the plurality of the etch through regions and the etch stop region;
etching the stack to form a plurality of openings through the stack and through the etch through regions to expose the sacrificial feature, such that the etch through material is etched preferentially compared to the first and the second materials of the stack;
removing the sacrificial feature through the plurality of openings;
and etching the stack to form a slit trench up to or only partially through the etch stop region, such that the first and the second materials of the stack are etched preferentially compared to the etch stop material,
wherein:
the plurality of etch through regions comprise a plurality of portions of a layer of the etch through material and the etch stop region comprises a substantially rail shaped region of the etch stop material embedded between the portions of the layer oft he etch through material; and
forming the plurality of etch through regions and the etch stop region comprises one of:
(a) forming a substantially rail shaped region of the etch stop material over the sacrificial feature, and forming the layer of the etch through material around the substantially rail shaped region;
(b) forming the layer of the etch through material over the sacrificial feature, forming a substantially rail shaped trench in the layer of the etch through material, and filling the trench with a substantially rail shaped region of the etch stop material; and
(c) forming the layer of the etch through material over the sacrificial feature, forming mask over the layer of the etch through material such that a substantially rail shaped region in the layer is exposed in the mask, and on implanting the exposed substantially rail shaped region in the layer of the etch through material to convert the etch through material to the etch stop material in the substantially rail shaped region.

2. The method of claim 1 , further comprising:
forming a blocking dielectric in the plurality of openings;
forming a charge storage layer over the blocking dielectric;
forming a tunnel dielectric over the charge storage layer; and
forming a semiconductor channel over the tunnel dielectric.

3. The method of claim 2 , wherein:
the semiconductor device comprises a monolithic, three dimensional vertical NAND string;
the plurality of openings comprise two memory openings extending to the same sacrificial feature; and
the slit trench is located between the two memory openings.

4. The method of claim 3 , wherein the step of removing the sacrificial feature through the two memory openings forms a hollow region extending substantially parallel to a major surface of the substrate which connects the two memory openings to form a hollow U-shaped pipe space comprising the two memory openings extending substantially perpendicular to the major surface of the substrate connected by the hollow region.

5. The method of claim 4 , wherein forming the semiconductor channel comprises forming the semiconductor channel in the hollow U-shaped pipe space such that the semiconductor channel has a U-shaped side cross section, comprising:
two wing portions which extend substantially perpendicular to the major surface of the substrate above the etch stop region;
a connecting portion which extends substantially parallel to the major surface of the substrate below the etch stop region and which connects the two wing portions; and
the semiconductor channel has a cross section of two circles when viewed from above.

6. The method of claim 5 , wherein:
the etch through material is etched at a higher rate compared to the first and the second materials of the stack during the step of etching the stack to form the plurality of openings;
the first and the second materials of the stack are etched at a higher rate compared to the etch stop material during the step of etching the stack to form the slit trench;
the plurality of etch through regions and the etch stop region are located in a same horizontal plane above both the major surface of the substrate and the sacrificial feature, but below the stack;
the etch through material in the plurality of etch through regions and the etch stop material in the etch stop region form a substantially planar upper surface over which the stack is formed;
the first material comprises a conductive or semiconductor control gate material; and
the second material comprises an insulating material.

7. The method of claim 6 , wherein:
a source electrode contacts the first wing;
drain electrode contacts the second wing;
the etch stop material comprises aluminum oxide, aluminum nitride, aluminum oxynitride, hafnium oxide, tantalum oxide, boron nitride or boron carbide or combinations thereof;
the etch through material comprises silicon germanium, amorphous silicon, amorphous carbon, silicon carbide, germanium, tungsten or tungsten silicide or combinations thereof;
the first material comprises polysilicon;
the second material comprises silicon oxide, silicon nitride or silicon oxynitride; and
the sacrificial feature comprises amorphous carbon, amorphous silicon or silicon nitride.

8. The method of claim 7 , wherein the step of etching the stack to form the slit trench occurs after the step of etching the stack to form the plurality of openings to form an air gap slit trench which separates the two wing portions.

9. The method of claim 7 , wherein the step of etching the stack to form the slit trench occurs before the step of etching the stack to form the plurality of openings, and further comprising:
filling the slit trench with a sacrificial material;
removing the sacrificial feature while the slit trench is filled with the sacrificial material; and
removing the sacrificial material from the slit trench after the step of removing the sacrificial feature to form an air gap slit trench which separates the two wing portions.

10. The method of claim 1 , wherein:
etching the stack to form the plurality of openings comprises reactively ion etching the plurality of openings through the stack and through the etch through material in the plurality of etch through regions using a first mask;
removing the sacrificial feature comprises selectively wet etching the sacrificial feature through the plurality of openings; and
etching the stack to form the slit trench comprises reactively ion etching the slit trench through the stack using a second mask different from the first mask.

11. The method of claim 1 , wherein:
etching the stack to form the plurality of openings comprises reactively ion etching the plurality of openings through the stack up to or only partially through the etch through material in the plurality of etch through regions using a first mask;
removing the sacrificial feature comprises selectively wet etching both the sacrificial feature and the etch through material via the plurality of openings in a same selective wet etching step;
sacrificial feature and the etch through material comprise the same material or a different material from each other; and
etching the stack to form the slit trench comprises reactively ion etching the slit trench through the stack using a second mask different from the first mask.

12. The method of claim 1 , wherein a width of the plurality of openings through the stack is

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Makala Raghuveer S
• Alsmeier Johann
• Lee Yao-Sheng
• Terahara Masanori
• Watatani Hirofumi
• Pachamuthu Jayavel

Classifications

• H10D88/01

  Manufacture or treatment · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D84/038 Primary

  using silicon technology, e.g. SiGe · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic