Method for processing a semiconductor workpiece and semiconductor workpiece

Patent metadata

Field	Value
Publication number	US-9627335-B2
Application number	US-201414272535-A
Country	US
Kind code	B2
Filing date	May 8, 2014
Priority date	May 8, 2014
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization layer over a semiconductor workpiece; patterning the first metallization layer; and depositing a second metallization layer over the patterned first metallization layer, wherein depositing the second metallization layer includes an electroless deposition process including immersing the patterned first metallization layer in a metal electrolyte.

First claim

What is claimed is:

1. A method for processing a semiconductor workpiece, comprising:
depositing a first metallization layer over a semiconductor workpiece;
patterning the first metallization layer;
depositing a third metallization layer over the semiconductor workpiece and patterning the third metallization layer, wherein depositing the first metallization layer over the semiconductor workpiece comprises depositing the first metallization layer over the third metallization layer; and
depositing a second metallization layer over the patterned first metallization layer, wherein depositing the second metallization layer comprises an electroless deposition process comprising immersing the patterned first metallization layer in a metal electrolyte, wherein the second metallization layer is not subsequently patterned after deposition;
wherein depositing the second metallization layer over the patterned first metallization layer comprises covering a top side and all sidewalls of the patterned first metallization layer and all sidewalls of the patterned third metallization layer with the second metallization layer, and
wherein the semiconductor workpiece comprises an electrically conductive area and the third metallization layer is deposited directly on the electrically conductive area,
wherein the second metallization layer is a final metallization layer comprising gold, and the first metallization layer comprises nickel vanadium, and the third metallization layer comprises titanium.

2. The method of claim 1 , wherein depositing the first metallization layer comprises a physical vapor deposition process.

3. The method of claim 1 , wherein immersing the patterned first metallization layer in a metal electrolyte comprises:
immersing the patterned first metallization layer in an immersion bath comprising the metal electrolyte.

4. The method of claim 3 , wherein the immersion bath further comprises a chemically reducing agent.

5. The method of claim 1 , wherein patterning the first metallization layer comprises etching the first metallization layer.

6. The method of claim 5 , wherein etching the first metallization layer comprises wet-chemically etching the first metallization layer.

7. The method of claim 1 , wherein depositing the third metallization layer comprises a physical vapor deposition process.

8. The method of claim 1 , wherein patterning the third metallization layer comprises patterning the third metallization layer after patterning the first metallization layer and before depositing the second metallization layer.

9. The method of claim 1 , wherein patterning the third metallization layer comprises etching the third metallization layer.

10. The method of claim 9 , wherein etching the third metallization layer comprises wet-chemically etching the third metallization layer.

11. The method of claim 1 , further comprising:
at least one of sintering, soldering, or bonding with the second metallization layer.

12. The method of claim 1 , further comprising:
wherein the semiconductor workpiece comprises a first insulating layer so that the electrically conductive area is disposed directly on the first insulating layer.

13. The method of claim 12 , further comprising:
wherein the semiconductor workpiece comprises a second insulating layer disposed adjacent to and partially on the electrically conductive area and directly on the first insulating layer,
wherein a portion of the first, second, and third metallization layers overhang a portion of the second insulating layer.

14. The method of claim 13 , wherein a portion of the second metallization layer and a portion of the third metallization layer contact the second insulating layer.

15. The method of claim 13 , wherein the surface of the second insulating layer facing away from the first insulating is higher than a surface of the electrically conductive layer facing away.

16. The method of claim 1 , wherein the electrically conductive layer is a contact pad.

17. A semiconductor workpiece, comprising:
a patterned third metallization layer disposed directly on an electrically conductive area of the semiconductor workpiece;
a patterned first metallization layer disposed directly on the third metallization layer; and
a second metallization layer covering a top side and sidewalls of the patterned first metallization layer and further covering sidewalls of the third metallization layer,
wherein the second metallization layer is formed by means of an electroless deposition process comprising immersing the patterned first metallization layer in a metal electrolyte, and
wherein the second metallization layer is a final metallization layer comprising gold, and the first metallization layer comprises nickel vanadium, and the third metallization layer comprises titanium.

Assignees

• Infineon Technologies Ag

Inventors

• Henneck Stephan
• Napetschnig Evelyn
• Pedone Daniel
• Weidgans Bernhard
• Faiss Simon
• Nikitin Ivan

Classifications

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/01955

  by using masks · CPC title

• H10W72/01953

  by etching · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title

• H10W72/01935

  by plating, e.g. electroless plating or electroplating · CPC title