Method of producing a large number of support apparatus which can be surface-mounted, arrangement of a large number of support apparatus which can be surface-mounted, and support apparatus which can be surface-mounted

Patent metadata

Field	Value
Publication number	US-9627304-B2
Application number	US-201315029693-A
Country	US
Kind code	B2
Filing date	Oct 17, 2013
Priority date	Oct 17, 2013
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A method of producing a multiplicity of surface-mountable carrier devices includes: A) providing a carrier plate having a first main face and a second main face located opposite the first main face, B) applying an electrically conductive layer to the first main face, C) applying a solder resist mask to a side of the electrically conductive layer remote from the carrier plate, wherein a multiplicity of adjoining regions are formed on the electrically conductive layer by the solder resist mask, D) applying a solder material to the solder resist mask and the electrically conductive layer, wherein the solder resist mask and the electrically conductive layer are at least partially covered by the solder material, and E) singulating the carrier plate and the electrically conductive layer along and through the solder resist mask and the solder material, wherein the solder material remains at least partially on the solder resist mask.

First claim

We claim:

1. A method of producing a multiplicity of surface-mountable carrier devices comprising:
A) providing a carrier plate having a first main face and a second main face located opposite the first main face;
B) applying an electrically conductive layer to the first main face of the carrier plate;
C) applying a solder resist mask to a side of the electrically conductive layer remote from the carrier plate, wherein a multiplicity of adjoining regions are formed on the electrically conductive layer by the solder resist mask;
D) applying a solder material to the solder resist mask and the electrically conductive layer, wherein the solder resist mask and the electrically conductive layer are covered by the solder material at least in places; and
E) singulating the carrier plate and the electrically conductive layer along and through the solder resist mask and the solder material, wherein the solder material remains on the solder resist mask at least in places.

2. The method according to claim 1 , wherein,
after step E, the surface-mountable carrier device is heated,
the solder material flows from the solder resist mask in the direction of the electrically conductive layer,
the solder material is delimited in the lateral direction by the solder resist mask, and
a face of the solder resist mask remote from the carrier plate is freed of the solder material.

3. An arrangement of a multiplicity of surface-mountable carrier devices comprising:
a carrier plate having a first main face and a second main face located opposite the first main face;
an electrically conductive layer;
a solder resist mask; and
a solder material, wherein
the electrically conductive layer completely covers the first main face of the carrier plate,
the solder resist mask is arranged on a side of the electrically conductive layer remote from the carrier plate,
side walls of the solder resist mask are at a spacing (A) in relation to one another in a lateral direction and the electrically conductive layer is free of the solder resist mask at least in places, and
the solder material from a side remote from the carrier plate covers the electrically conductive layer and the solder resist mask at least in places, wherein the solder material is in direct contact with the electrically conductive layer and the solder resist mask.

4. A surface-mountable carrier device comprising:
a carrier plate having a first main face and a second main face located opposite the first main face;
the first main face connects to the second main face via a side face;
an electrically conductive layer;
a solder resist mask; and
a solder material, wherein
the electrically conductive layer covers the first main face of the carrier plate at least in places and the electrically conductive layer terminates flush with the side face of the carrier plate,
the solder resist mask is arranged on a side of the electrically conductive layer remote from the carrier plate,
side walls of the solder resist mask are at a spacing (A) in relation to one another in a lateral direction and the electrically conductive layer is free of the solder resist mask at least in places, wherein
the side walls of the solder resist mask terminate flush with the side face of the carrier plate and the electrically conductive layer,
the solder material is in direct contact with the electrically conductive layer at least in places, wherein
the solder resist mask is free of the solder material on a face remote from the carrier plate,
the solder resist mask comprises an electrically conductive material,
the solder resist mask delimits the solder material in the lateral direction, and
the solder material protrudes beyond the solder resist mask in the vertical direction (V) in places.

5. The surface-mountable carrier device according to claim 4 , wherein the side face of the carrier plate has traces of a physical and/or mechanical material removal.

6. The surface-mountable carrier device according to claim 4 , wherein the solder resist mask comprises chromium.

7. The surface-mountable carrier device according to claim 4 , wherein the solder resist mask has a lattice shaped structure.

8. The surface-mountable carrier device according to claim 4 , wherein the spacing (A) between the side walls of the solder resist mask in the lateral direction is at least 200 μm.

9. The surface-mountable carrier device according to claim 4 , wherein an optoelectronic semiconductor chip is arranged on the second main face of the carrier plate.

10. The surface-mountable carrier device according to claim 4 , wherein the carrier plate comprises at least one of Si, SiC and Ge.

11. The surface-mountable carrier device according to claim 4 , wherein the solder material comprises an eutectic Au/Sn alloy.

12. The surface-mountable carrier device according to claim 4 , wherein the electrically conductive layer comprises an Au and/or Ag.

Assignees

• Osram Opto Semiconductors Gmbh

Inventors

• Lim Choo Kean
• Chang Chee Jia
• Or Choon Keat

Classifications

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W70/093 Primary

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title