Metastability error reduction in asynchronous successive approximation analog to digital converter

Patent metadata

Field	Value
Publication number	US-9621179-B1
Application number	US-201615067293-A
Country	US
Kind code	B1
Filing date	Mar 11, 2016
Priority date	Mar 11, 2016
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

Various aspects facilitate error reduction for an analog to digital converter (e.g., due to metastability). A digital to analog converter generates a scaled reference voltage based on a reference voltage. A comparator component performs a comparison between an input voltage and the scaled reference voltage based on a defined period of time to perform the comparison.

First claim

What is claimed is:

1. An analog to digital converter system, comprising:
a digital to analog converter configured for generating a scaled reference voltage based on a reference voltage; and
a comparator component configured for performing a comparison between an input voltage and the scaled reference voltage based on a period of time that defines a maximum amount of time for the comparator component to perform the comparison, wherein a digital value previously stored in a register is outputted as a digital representation of the input voltage in response to a determination that the comparison is not completed within the period of time that defines the maximum amount of time for the comparator component to perform the comparison.

2. The analog to digital converter system of claim 1 , wherein the comparator is configured for stopping the comparison performed by the comparator component in response to a timer signal received from a timer component.

3. The analog to digital converter system of claim 1 , wherein the determination is a first determination, and wherein the register is configured for storing comparator output associated with the comparison in response to a second determination that the comparison is completed within the period of time.

4. The analog to digital converter system of claim 3 , further comprising a timer component configured for transmitting a timer signal to a control component in response to the second determination that the comparison is completed within the period of time.

5. The analog to digital converter system of claim 1 , wherein an analog to digital conversion process for the input voltage is stopped in response to the determination that the comparison is not completed within the period of time due to the comparator component being in a metastable state.

6. The analog to digital converter system of claim 1 , wherein the register is not updated and the digital value previously stored in the register is outputted as the digital representation of the input voltage in response to the determination that the comparison is not completed within the period of time.

7. The analog to digital converter system of claim 1 , wherein the digital to analog converter comprises a plurality binary-weighted capacitors or a plurality of thermometer-weighted capacitors.

8. The analog to digital converter system of claim 1 , wherein the input voltage and the scaled reference voltage are analog voltage signals.

9. An error reduction method, comprising:
receiving an input voltage to be converted into a digital value;
generating a scaled reference voltage based on a reference voltage;
performing a comparison between the input voltage and the scaled reference voltage based on a period of time that defines a maximum amount of time for performing the comparison; and
outputting data previously stored in a successive approximation register as a digital representation of the input voltage in response to a determination that the comparison is not completed within the period of time that defines the maximum amount of time for the performing the comparison.

10. The error reduction method of claim 9 , wherein performing the comparison comprises starting the comparison in response to a command signal.

11. The error reduction method of claim 9 , further comprising storing an output value associated with the comparison in response to another determination that the comparison is completed within the period of time.

12. The error reduction method of claim 9 , further comprising transmitting a timer signal to the successive approximation register in response to another determination that the comparison is completed within the period of time.

13. The error reduction method of claim 9 , wherein the outputting comprises stopping an analog to digital conversion process associated with the input voltage in response to the determination that the comparison is not completed within the period of time.

14. The error reduction method of claim 9 , wherein the outputting comprises outputting a digital value that is different than a true digital representation of the input voltage in response to a determination that the comparison is not completed within the period of time.

15. A successive approximation register, comprising:
a register configured for storing a digital value provided by a comparator that compares an input voltage to a scaled reference voltage generated by a digital to analog converter; and
a control component configured for controlling a binary search algorithm associated with the digital to analog converter, wherein a set of digital values previously stored in the register is employed as a digital representation of the input voltage in response to a determination that the comparator has not completed a comparison between the input voltage and the scaled reference voltage within an interval of time due to the comparator being in a metastable state, and wherein the interval of time defines a maximum amount of time for the comparator to perform the comparison.

16. The successive approximation register of claim 15 , wherein an analog to digital conversion process for the input voltage is stopped in response to the determination that the comparator has not completed the comparison between the input voltage and the scaled reference voltage within the interval of time.

17. The successive approximation register of claim 15 , wherein the register is configured for storing the digital value provided by the comparator in response to another determination that the comparator has completed the comparison between the input voltage and the scaled reference voltage within the interval of time.

18. The successive approximation register of claim 15 , wherein the control component is configured for receiving a timer signal in response to another determination that the comparison has completed the comparison between the input voltage and the scaled reference voltage within the interval of time.

19. The successive approximation register of claim 15 , wherein the comparator is configured for starting the comparison in response to a timer signal.

20. The successive approximation register of claim 15 , wherein the scaled reference voltage is generated based on a reference voltage.

Assignees

• Applied Micro Circuits Corp

Inventors

• Maulik Prabir
• Govind Nanda

Classifications

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/466 Primary

  using switched capacitors · CPC title

• H03M1/46

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03M1/0863 Primary

  of switching transients, e.g. glitches · CPC title