Adaptive delay based asynchronous successive approximation analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-9258008-B2
Application number	US-201414230370-A
Country	US
Kind code	B2
Filing date	Mar 31, 2014
Priority date	Mar 31, 2014
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

An asynchronous SAR ADC to convert an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.

First claim

What is claimed is:

1. An analog-to-digital converter, comprising:
an input configured to receive an analog signal;
a conversion circuit configured to convert the analog signal to a digital representation of the analog signal; and
a delay circuit coupled to the conversion circuit and configured to trigger the conversion circuit with a logic signal;
wherein the delay circuit comprises a first comparator having a first input and second input, each input coupled to the conversion circuit, the first comparator configured to generate the logic signal at a variable interval that is inversely proportional to a voltage difference between a signal on the first input and a signal on the second input.

2. The analog-to-digital converter of claim 1 , further comprising a successive approximation register analog-to-digital converter.

3. The analog-to-digital converter of claim 1 , wherein the conversion circuit comprises:
a sample and hold circuit coupled to the input;
a digital-to-analog converter coupled to the sample and hold circuit;
a second comparator coupled to the digital-to-analog converter; and
a successive approximation register coupled to the second comparator.

4. The analog-to-digital converter of claim 1 , wherein the first comparator comprises a continuous-time comparator.

5. The analog-to-digital converter of claim 1 , wherein the first comparator comprises a comparator having a linear gain function.

6. The analog-to-digital converter of claim 1 , wherein the first comparator comprises an exponential gain function.

7. The analog-to-digital converter of claim 1 , further comprising a control circuit coupled to the conversion circuit and configured to bypass the delay circuit after a condition is met.

8. The analog-to-digital converter of claim 7 , wherein the condition comprises determining a threshold number of bits in the digital representation of the analog signal.

9. A method, comprising:
receiving an signal at an input;
repeatedly determining at variable intervals if a magnitude of the signal exceeds a threshold;
wherein each variable interval is inversely proportional to a difference between the magnitude of the signal and the threshold.

10. The method of claim 9 , further comprising storing each determination as a logic value in a register after each determination.

11. The method of claim 10 , further comprising periodically outputting the contents of the register.

12. The method of claim 9 , further comprising repeatedly determining if a magnitude of the signal exceeds a threshold at a regular interval after a first number of determinations at variable intervals.

13. A method, comprising:
receiving an signal at an input;
repeatedly determining at variable intervals if a magnitude of the signal exceeds a threshold; and
repeatedly determining at a regular interval if the magnitude of the signal exceeds the threshold after a first number of determinations at said variable intervals has been made.

14. The method of claim 13 , further comprising determining each variable interval as inversely proportional to the difference between the magnitude of the signal and the threshold.

15. The method of claim 13 , further comprising storing each determination as a logic value in a register after each determination.

16. An analog to digital converter comprising:
an input configured to receive an analog signal;
a conversion circuit configured to convert the analog signal to a digital representation of the analog signal; and
a delay circuit coupled to the conversion circuit and configured to trigger the conversion circuit to generate bits in the digital representation at variable intervals; and
a control circuit coupled to the conversion circuit and configured to bypass the delay circuit after a condition is met and trigger the conversion circuit to generate further bits in the digital representation at regular intervals.

17. The analog-to-digital converter of claim 16 , wherein the condition comprises a threshold number of bits in the digital representation of the analog signal being generated by the conversion circuit.

18. An analog-to-digital converter, comprising:
an input configured to receive an analog signal;
a conversion circuit configured to convert the analog signal to a digital representation of the analog signal; and
a delay circuit coupled to the conversion circuit and configured to trigger the conversion circuit at variable intervals;
wherein the delay circuit comprises a first comparator having a first input and second input, each input coupled to the conversion circuit, the first comparator comprising an exponential gain function and being configured to generate a logic signal in response to a voltage difference between a signal on the first input and a signal on the second input.

19. The analog-to-digital converter of claim 18 , wherein the conversion circuit comprises:
a sample and hold circuit coupled to the input;
a digital-to-analog converter coupled to the sample and hold circuit;
a second comparator coupled to the digital-to-analog converter; and
a successive approximation register coupled to the second comparator.

20. The analog-to-digital converter of claim 18 , further comprising a control circuit coupled to the conversion circuit and configured to bypass the delay circuit after a condition is met.

21. The analog-to-digital converter of claim 20 , wherein the condition comprises determining a threshold number of bits in the digital representation of the analog signal.

Assignees

• St Microelectronics Int Nv

Inventors

• Singh Pratap Narayan
• Kumar Ashish Sharma
• Debnath Chandrajit
• Malik Rakesh

Classifications

• H03M1/0695

  using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/00

  Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00) · CPC title

• H03M1/125 Primary

  Asynchronous, i.e. free-running operation within each conversion cycle · CPC title

• H03M1/462 Primary

  Details of the control circuitry, e.g. of the successive approximation register · CPC title