Enhanced resolution successive-approximation register analog-to-digital converter and method

Patent metadata

Field	Value
Publication number	US-9252800-B1
Application number	US-201414462916-A
Country	US
Kind code	B1
Filing date	Aug 19, 2014
Priority date	Aug 19, 2014
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC) is provided that includes a digital-to-analog converter (DAC), a comparator and enhanced resolution SAR control logic. The DAC includes analog circuitry that is configured to convert an M-bit digital input to an analog output. The comparator includes a plurality of coupling capacitors. The enhanced resolution SAR control logic is configured to generate an M-bit approximation of an input voltage and to store a residue voltage in at least one of the coupling capacitors. The residue voltage represents a difference between the input voltage and the M-bit approximation of the input voltage. The enhanced resolution SAR control logic is further configured to generate an N-bit approximation of the input voltage based on the stored residue voltage, where N>M.

First claim

What is claimed:

1. An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC), comprising:
a digital-to-analog converter (DAC) comprising analog circuitry configured to convert an M-bit digital input to an analog output;
a comparator comprising a plurality of coupling capacitors; and
enhanced resolution SAR control logic configured to generate an M-bit approximation of an input voltage; to store a residue voltage in at least one of the coupling capacitors, wherein the residue voltage comprises a difference between the input voltage and the M-bit approximation of the input voltage; and to generate an N-bit approximation of the input voltage based on the stored residue voltage, where N>M;
wherein the residue voltage comprises a first residue voltage, and
wherein the enhanced resolution SAR control logic is further configured to receive a comparator output based on the input voltage added to the first residue voltage; to generate an M-bit approximation of the comparator output; to store a difference between the first residue voltage and a second residue voltage in at least one second coupling capacitor, wherein the second residue voltage comprises a difference between the input voltage and the M-bit approximation of the comparator output; and to generate the N-bit approximation of the input voltage based on the stored residue voltage by generating the N-bit approximation of the input voltage based on the stored first residue voltage and the stored difference between the first and second residue voltages.

2. An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC), comprising:
a digital-to-analog converter (DAC) comprising analog circuitry configured to convert an M-bit digital input to an analog output;
a comparator comprising a plurality of coupling capacitors; and
enhanced resolution SAR control logic configured to generate an M-bit approximation of an input voltage; to store a residue voltage in at least one of the coupling capacitors, wherein the residue voltage comprises a difference between the input voltage and the M-bit approximation of the input voltage; and to generate an N-bit approximation of the input voltage based on the stored residue voltage, where N>M;
wherein the comparator is further configured to receive the input voltage and the analog output and to generate a comparator output based on the input voltage and the analog output, and
wherein the enhanced resolution SAR control logic is further configured to generate the M-bit approximation of the input voltage based on the comparator output.

3. An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC), comprising:
a digital-to-analog converter (DAC) comprising analog circuitry configured to convert an M-bit digital input to an analog output;
a comparator comprising a plurality of coupling capacitors; and
enhanced resolution SAR control logic configured to generate an M-bit approximation of an input voltage; to store a residue voltage in at least one of the coupling capacitors, wherein the residue voltage comprises a difference between the input voltage and the M-bit approximation of the input voltage; and to generate an N-bit approximation of the input voltage based on the stored residue voltage, where N>M;
wherein the coupling capacitors comprise auto-zero capacitors.

4. An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC), comprising:
a digital-to-analog converter (DAC) comprising analog circuitry configured to convert an M-bit digital input to an analog output;
a comparator comprising a plurality of coupling capacitors; and
enhanced resolution SAR control logic configured to generate an M-bit approximation of an input voltage; to store a residue voltage in at least one of the coupling capacitors, wherein the residue voltage comprises a difference between the input voltage and the M-bit approximation of the input voltage; and to generate an N-bit approximation of the input voltage based on the stored residue voltage, where N>M;
wherein the coupling capacitors comprise pairs of differential capacitors.

5. A method for increasing the resolution of a SAR ADC, comprising:
generating an M-bit approximation of an input voltage;
determining a residue voltage based on the input voltage and the M-bit approximation of the input voltage;
storing the residue voltage in at least one coupling capacitor; and
generating an N-bit approximation of the input voltage based on the stored residue voltage, wherein N=M+1;
wherein storing the residue voltage in at least one coupling capacitor comprises storing a first scaled version of the residue voltage in a first coupling capacitor and a second scaled version of the residue voltage in a second coupling capacitor.

6. The method of claim 5 , wherein the first coupling capacitor comprises a first pair of differential capacitors and the second coupling capacitor comprises a second pair of differential capacitors.

7. The method of claim 5 , further comprising generating a comparator output based on the first scaled version of the residue voltage and the second scaled version of the residue voltage.

8. The method of claim 7 , further comprising determining an output voltage based on the comparator output.

9. The method of claim 8 , wherein generating the N-bit approximation of the input voltage based on the stored residue voltage comprises generating the N-bit approximation of the input voltage based on the M-bit approximation of the input voltage and the output voltage.

10. The method of claim 9 ,
wherein the comparator output is a multiple of 1-2V res , where V res is the stored residue voltage,
wherein the output voltage is 0 when the comparator output is greater than zero and the output voltage is 1 when the comparator output is less than or equal to zero, and
wherein the N-bit approximation of the input voltage is provided by 2V DAC +V out , where V DAC is the M-bit approximation of the input voltage and V out is the output voltage.

11. A method for increasing the resolution of a SAR ADC, comprising:
generating an M-bit approximation of an input voltage;
determining a first residue voltage based on the input voltage and the M-bit approximation of the input voltage;
storing the first residue voltage in a first coupling capacitor;
determining a second residue voltage based on the input voltage and the M-bit approximation of the input voltage;
storing a difference between the first and second residue voltages in a second coupling capacitor and a third coupling capacitor; and
generating an N-bit approximation of the input voltage based on the stored difference, wherein N=M+2.

12. The method of claim 11 , wherein storing the difference between the first and second residue voltages comprises storing a first scaled version of the difference in the second coupling capacitor and a second scaled version of the difference in the third coupling capacitor.

13. The method of claim 12 , wherein the first coupling capacitor comprises a first pair of differential capacitors, the second coupling capacitor comprises a second pair of differential capacitors, and the third coupling capacitor comprises a third pair of differential capacitors.

14. The method of claim 12 , further comprising generating a final comparator output based on the first scaled version of the difference and the second scaled version of the difference.

15. The method of claim 14 , further comprising determining an output voltage based on the final comparator output.

Assignees

• Texas Instruments Inc

Inventors

• Park Joonsung
• Nagaraj Krishnaswamy
• Ash Mikel

Classifications

• H03M1/20 Primary

  Increasing resolution using an n bit system to obtain n + m bits · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/162

  the steps being performed sequentially in a single stage, i.e. recirculation type (H03M1/161 takes precedence) · CPC title