Systems and methods for an adjustable filter engine

Patent metadata

Field	Value
Publication number	US-9621131-B2
Application number	US-201414282798-A
Country	US
Kind code	B2
Filing date	May 20, 2014
Priority date	Apr 26, 2010
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

Systems and methods are provided for an adjustable filter engine. In particular, an electronic system is provided that can include a focus module, memory, and control circuitry. In some embodiments, the focus module can include an adjustable filter engine and a motor. By using the adjustable filter engine to generate a filter with a large number of filter coefficients, the control circuitry can accommodate a variety of system characteristics. For example, by generating a set of cumulative coefficients and re-arranging the order of the cumulative coefficients, the control circuitry can reduce the bit-width requirements of the adjustable filter engine hardware. For instance, the control circuitry can reduce the number of multipliers required to perform a convolution between an updated filter and one or more input signals. In some embodiments, the updated filter can be generated to reduce oscillations of the motor movement due to a new position request.

First claim

What is claimed is:

1. An electronic system for generating a filter comprising:
memory for storing a set of cumulative coefficients, the memory comprising a set of registers configured to store a plurality of parameters, wherein a first register of the set of registers comprises a current position of a motor, and a second register of the set of register comprises a next position of the motor;
an adjustable filter engine comprising:
a first multiplier; and
a coefficient address generator for generating at least one coefficient address based on one or more of the plurality of parameters; and
control circuitry, wherein the control circuitry is operative to:
read a cumulative coefficient of the set of cumulative coefficients from the memory based on the at least one coefficient address;
multiply the cumulative coefficient and the current position using the first multiplier to obtain a weighted current position; and
generate an output of the filter corresponding to the cumulative coefficient based at least in part on the weighted current position and a weighted next position formed from the next position stored in the second register.

2. The electronic system of claim 1 , wherein the one or more of the plurality of parameters comprises at least a start address, a step size, and a number of cumulative coefficients.

3. The electronic system of claim 1 , wherein the memory is a static random access memory (“SRAM”).

4. The electronic system of claim 1 , wherein the adjustable filter engine further comprises a first adder, and wherein the control circuitry is further operative to subtract the cumulative coefficient from a value of one to obtain an adjusted cumulative coefficient using the first adder.

5. The electronic system of claim 4 , wherein the adjustable filter engine further comprises a second multiplier, and wherein the control circuitry is further operative to multiply the adjusted cumulative coefficient and the next position using the second multiplier to obtain the weighted next position.

6. The electronic system of claim 5 , wherein the adjustable filter engine further comprises a second adder, and wherein the control circuitry is further operative to generate the output of the filter by adding the weighted current position and the weighted next position using the second adder.

7. A semiconductor chip comprising:
memory comprising at least one register; and
control circuitry, wherein the control circuitry is operative to:
generate a set of cumulative coefficients, wherein each cumulative coefficient of the set of cumulative coefficients corresponds to an accumulation of one or more filter coefficients of a finite impulse response (“FIR”) filter;
determine at least one parameter of the set of cumulative coefficients;
program the at least one parameter into the at least one register of the memory; and
program the set of cumulative coefficients in the memory;
wherein the control circuitry is also operative to:
access one or more cumulative coefficients of the set of cumulative coefficients from the memory;
generate a filter using the one or more cumulative coefficients; and
perform a convolution between the finite impulse filter and a current position of the motor and a next position of the motor.

8. The chip of claim 7 , wherein the control circuitry is further operative to determine a sampling period of the set of cumulative coefficients based at least in part on a system clock rate and a sampling rate of the FIR filter.

9. The chip of claim 7 , wherein the control circuitry is operative to program a step size of the set of cumulative coefficients into the at least one register of the memory.

10. The chip of claim 7 , further comprising an adjustable filter engine, wherein the adjustable filter engine comprises two multipliers.

11. A semiconductor chip comprising:
memory comprising at least one register wherein the at least one register comprises a first register corresponding to a current position of a motor and a second register corresponding to a next position of the motor;
an adjustable filter engine, wherein the adjustable filter engine comprises two multipliers; and,
control circuitry, wherein the control circuitry is operative to:
generate a set of cumulative coefficients, wherein each cumulative coefficient of the set of cumulative coefficients corresponds to an accumulation of one or more filter coefficients of a finite impulse response (“FIR”) filter; determine at least one parameter of the set of cumulative coefficients; and
program the at least one parameter into the at least one register of the memory; and program the set of cumulative coefficients in the memory, and wherein the control circuitry is further operative to:
access one or more cumulative coefficients of the set of cumulative coefficients from the memory;
generate a filter using the one or more cumulative coefficients; and
perform a convolution between the filter and the current position of the motor and the next position of the motor using the two multipliers.

12. The chip of claim 11 , wherein the control circuitry is further operative to: adjust the at least one parameter of the set of cumulative coefficients; and access the one or more cumulative coefficients of the set of cumulative coefficients from the memory based at least in part on the at least one adjusted parameter.

13. The chip of claim 12 , wherein the control circuitry is further operative to: adjust a sampling period of the set of cumulative coefficients; and program the adjusted sampling period into the at least one register of the memory.

14. The chip of claim 12 , wherein the control circuitry is further operative to: adjust a step size of the set of cumulative coefficients; and program the adjusted step size into the at least one register of the memory.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Wu Chihsin

Classifications

• H03H21/0012 Primary

  Digital adaptive filters · CPC title

• H03H17/0294 Primary

  Variable filters; Programmable filters · CPC title