Adaptive filtering method and system based on error sub-band

Patent metadata

Field	Value
Publication number	US-9419826-B2
Application number	US-201514671810-A
Country	US
Kind code	B2
Filing date	Mar 27, 2015
Priority date	Sep 27, 2012
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

The present invention discloses an adaptive filtering method and system based on an error sub-band. The present invention includes performing analysis filtering processing on an error signal and an input signal to obtain an error sub-band signal and an input sub-band signal respectively; and performing calculation according to the input sub-band signal and the error sub-band signal to obtain a new adaptive filtering weight, and updating a weight in an adaptive filter.

First claim

What is claimed is:

1. An adaptive filtering method based on an error sub-band, the method comprising:
receiving, by an adaptive filter, an input signal;
performing adaptive filtering processing on the input signal according to an adaptive filtering weight currently stored in the adaptive filter, so as to obtain an adaptive filtering signal, and transmitting the adaptive filtering signal to a subtractor, wherein the adaptive filter has L branches that comprise a first branch to an L th branch, and each branch has M multipliers, one ingress port, and one egress port, wherein L is a positive integer greater than 1 and M is a positive integer greater than 1;
receiving, by the subtractor, a reference signal and the adaptive filtering signal;
performing a calculation according to the reference signal and the adaptive filtering signal to obtain an error signal;
transmitting the error signal to an error sub-band filter, wherein the reference signal is a signal generated after the input signal passes through a real channel;
receiving, by the error sub-band filter, the error signal;
performing sub-band analysis filtering processing on the error signal to obtain an error sub-band signal;
transmitting the error sub-band signal to an adaptive weight updater;
receiving, by an input signal analysis filter, the input signal;
performing sub-band analysis filtering processing on the input signal to obtain an input sub-band signal;
transmitting the input sub-band signal to the adaptive weight updater;
receiving, by the adaptive weight updater, the error sub-band signal and the input sub-band signal;
performing calculation according to the error sub-band signal and the input sub-band signal to obtain a new adaptive filtering weight; and
replacing the adaptive filtering weight currently stored in the adaptive filter with the new adaptive filtering weight.

2. The method according to claim 1 , wherein the adaptive filter has a first branch of the L branches;
wherein M first multipliers, M−1 adders, and M−1 M-clock delayers are disposed in the first branch;
wherein the M first multipliers comprise a first multiplier 0 to a first multiplier M−1;
wherein the M−1 adders comprise an adder 1 to an adder M−1;
wherein the M−1 M-clock delayers comprise an M-clock delayer 1 to an M-clock delayer M−1;
wherein each delayer has one ingress port and one egress port;
wherein each first multiplier has one ingress port and one egress port;
wherein each adder has two ingress ports and one egress port;
wherein an ingress port of the first branch is connected to ingress ports of the first multiplier 0 to the first multiplier M−1;
wherein an egress port of the first multiplier 0 is connected to an ingress port of the M-clock delayer 1;
wherein an egress port of each of a first multiplier 1 to the first multiplier M−1 is connected to one ingress port of each of the adder 1 to the adder M−1; and
wherein an egress port of each of the M-clock delayer 1 to the M-clock delayer M−1 is connected to the other ingress port of each of the adder 1 to the adder M−1.

3. The method according to claim 2 , wherein receiving, by the adaptive filter, the input signal and performing adaptive filtering processing on the input signal according to the adaptive filtering weight currently stored in the adaptive filter, so as to obtain an adaptive filtering signal, comprises:
in the first branch, receiving, by each of the first multiplier 0 to the first multiplier M−1, the input signal through the ingress port of the first branch;
performing multiplication on the input signal according to an adaptive filtering weight stored in each of the first multipliers, to obtain a multiplier output signal generated by each of the first multiplier 0 to the first multiplier M−1;
outputting, by each of the first multiplier 0 to the first multiplier M−1 through an egress port of each of the first multiplier 0 to the first multiplier M−1, the multiplier output signal generated by each of the first multiplier 0 to the first multiplier M−1;
performing, by each of the M-clock delayer 1 to the M-clock delayer M−1, M-clock delay processing on a signal received at an ingress port of each of the M-clock delayer 1 to the M-clock delayer M−1, to obtain an M-clock delay signal generated by each of the M-clock delayer 1 to the M-clock delayer M−1;
outputting, by each of the M-clock delayer 1 to the M-clock delayer M−1 through the egress port of each of the M-clock delayer 1 to the M-clock delayer M−1, the M-clock delay signal generated by each of the M-clock delayer 1 to the M-clock delayer M−1;
performing, by the adder 1 to the adder M−1, addition processing on signals received through two ingress ports corresponding to each of the adder 1 to the adder M−1, to obtain an adder output signal generated by each of the adder 1 to the adder M−1; and
outputting, by each of the adder 1 to the adder M−1 through an egress port corresponding to each of the adder 1 to the adder M−1, the adder output signal generated by each of the adder 1 to the adder M−1.

4. The method according to claim 1 , wherein one (L−1)-clock delayer, M second multipliers, M−1 adders, and M−1 M-clock delayers are disposed in the L th branch;
wherein the M second multipliers in the L th branch are a second multiplier 0 to a second multiplier M−1;
wherein the M−1 adders are an adder 1 to an adder M−1;
wherein the M−1 M-clock delayers are an M-clock delayer 1 to an M-clock delayer M−1;
wherein each delayer has one ingress port and one egress port;
wherein each second multiplier has one ingress port and one egress port;
wherein each adder has two ingress ports and one egress port; and
wherein, in the L th branch, an ingress port of the L th branch is connected to an ingress port of the (L−1)-clock delayer, an egress port of the (L−1)-clock delayer is connected to ingress ports of all second multipliers, an egress port of the second multiplier 0 is connected to an ingress port of the M-clock delayer 1, an egress port of each of a second multiplier 1 to the second multiplier M−1 is connected to one ingress port of each of the adder 1 to the adder M−1, and an egress port of each of the M-clock delayer 1 to the M-clock delayer M−1 is connected to the other ingress port of each of the adder 1 to the adder M−1.

5. The method according to claim 4 , wherein receiving, by the adaptive filter, the input signal, performing the adaptive filtering processing on the input signal according to the adaptive filtering weight currently stored in the adaptive filter comprises:
in the L th branch, receiving, by the (L−1)-clock delayer, the input signal through the ingress port of the (L−1)-clock delayer;
performing (L−1)-clock delay processing on the input signal to generate an (L−1)-clock delay signal;
outputting, by the (L−1)-clock delayer, the (L−1)-clock delay signal through the egress port of the (L−1)-clock delayer;
receiving, by each of the second multiplier 0 to the second multiplier M−1 in the L th branch, the (L−1)-clock delay signal through the ingress port of the L th branch;
performing multiplication on the (L−1)-clock delay signal according to an adaptive filtering weight stored in each of the second multipliers, to obtain a multiplier output signal generated by each of the second multiplier 0 to the second multiplier M−1;
outputting, by each of the second multiplier 0 to the second multiplier M−1 through an egress port of each of the second multiplier 0 to the second multiplier M−1, the multiplier output signal generated by each of the second multiplier 0 to the second multiplier M−1;
performing, by each of the M-clock delayer 1 to the M-clock delayer M−1, M-clock delay processing on a signal received at an ingress port of each of the M-clock delayer 1 to the M-clock delayer M−1, to obtain a d

Assignees

• Huawei Tech Co Ltd

Inventors

• Shi Dongyuan
• He Dongmei
• Cai Meng

Classifications

• H04L25/03057 Primary

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• H04L2025/03617

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• H04L25/03

  Shaping networks in transmitter or receiver, e.g. adaptive shaping networks · CPC title

• H03H2021/0041

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• H03H21/0012

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