Array based fabrication of power semiconductor package with integrated heat spreader

Patent metadata

Field	Value
Publication number	US-9620475-B2
Application number	US-201414546854-A
Country	US
Kind code	B2
Filing date	Nov 18, 2014
Priority date	Dec 9, 2013
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

In one implementation, a method of fabricating a power semiconductor package is disclosed. The method includes providing a conductive carrier array including a plurality of power modules held together with connecting bars, where each of the plurality of power modules includes a control transistor, a sync transistor, and a driver IC. The method further includes overlying on the conductive carrier array a heat spreader array including a plurality of power electrode heat spreaders such that each of the plurality of power electrode heat spreaders couples a drain of the sync transistor to a source of the control transistor in each power module.

First claim

The invention claimed is:

1. A method of fabricating a power semiconductor package, said method comprising:
providing a conductive carrier array including a plurality of power modules held together with connecting bars, wherein each of said plurality of power modules includes a control transistor, a sync transistor and a driver IC; and
overlying on said conductive carrier array a heat spreader array that includes a plurality of power electrode heat spreaders, and in each power module of said plurality of power modules:
a drain of said sync transistor is electrically coupled to a sync drain carrier segment, a source of said sync transistor is electrically coupled to a sync source carrier segment and a gate of said sync transistor is electrically coupled to a sync gate carrier segment;
a drain of said control transistor is electrically coupled to a control drain carrier segment, a source of said control transistor is electrically coupled to said drain of said sync transistor and a gate of said control transistor is electrically coupled to a control gate carrier segment, wherein said source and said gate of said control transistor are positioned on a top surface of said control transistor, and said drain of said control transistor is positioned on a bottom surface of said control transistor; and
a corresponding power electrode heat spreader has a contact surface and is mechanically coupled along said contact surface to said drain of said sync transistor, said sync drain carrier segment and said source of said control transistor;
wherein said connecting bars provide electrical connection for said source or said gate of said sync transistor and facilitate array-based fabrication of the power semiconductor package to increase fabrication efficiency and reduce fabrication cost.

2. The method of claim 1 further comprising:
selectively applying a conductive adhesive to segments of said conductive carrier array and in each power module to said source of said control transistor and said drain of said sync transistor.

3. The method of claim 1 further comprising:
in each power module, coupling said gate of said control transistor to said control gate carrier segment.

4. The method of claim 3 , wherein said gate of said control transistor is coupled to said control gate carrier segment using a gate electrode heat spreader.

5. The method of claim 3 , wherein said gate of said control transistor is coupled to said control gate carrier segment using a wire bond.

6. The method of claim 1 further comprising:
singulating said conductive carrier array and said heat spreader array to form said power semiconductor package.

7. The method of claim 1 , wherein said driver IC is attached to a driver IC carrier segment.

8. The method of claim 1 , wherein said sync transistor and said control transistor are selected from the group consisting of a FET, an IGBT, and a HEMT.

9. The method of claim 1 , wherein said sync transistor and said control transistor are selected from the group consisting of a silicon FET and a GaN FET.

10. A method of fabricating a power semiconductor package, said method comprising:
providing a conductive carrier array including a plurality of power modules held together with connecting bars, wherein each of said plurality of power modules includes a control transistor, a sync transistor and a driver IC; and
overlying on said conductive carrier array a heat spreader array that includes a plurality of power electrode heat spreaders, and in each power module of said plurality of power modules:
said driver IC is electrically coupled to a driver IC carrier segment;
a drain of said sync transistor is electrically coupled to a sync drain carrier segment, a source of said sync transistor is electrically coupled to a sync source carrier segment and a gate of said sync transistor is electrically coupled to a sync gate carrier segment;
a drain of said control transistor is electrically coupled to a control drain carrier segment, a source of said control transistor is electrically coupled to said drain of said sync transistor and a gate of said control transistor is electrically coupled to a control gate carrier segment, wherein said source and said gate of said control transistor are positioned on a top surface of said control transistor, and said drain of said control transistor is positioned on a bottom surface of said control transistor; and
a corresponding power electrode heat spreader has a contact surface and is mechanically coupled along said contact surface to said drain of said sync transistor, said sync drain carrier segment and said source of said control transistor;
wherein said connecting bars provide electrical connection for said source or said gate of said sync transistor and facilitate array-based fabrication of the power semiconductor package to increase fabrication efficiency and reduce fabrication cost.

11. The method of claim 10 further comprising:
selectively applying a conductive adhesive to segments of said conductive carrier array and in each power module to said source of said control transistor and said drain of said sync transistor.

12. The method of claim 10 further comprising:
in each power module, coupling said gate of said control transistor to said control gate carrier segment.

13. The method of claim 12 , wherein said gate of said control transistor is coupled to said control gate carrier segment using a gate electrode heat spreader.

14. The method of claim 10 , wherein said sync transistor and said control transistor are selected from the group consisting of a FET, an IGBT, and a HEMT.

15. A power semiconductor package comprising:
a sync transistor having a drain on a top surface of said sync transistor, and a source and a gate on a bottom surface of said sync transistor, wherein connecting bars provide electrical connection for said source or said gate of said sync transistor and facilitate array-based fabrication of the power semiconductor package to increase fabrication efficiency and reduce fabrication cost;
wherein said drain of said sync transistor is electrically coupled to a sync drain carrier segment, said source of said sync transistor is electrically coupled to a sync source carrier segment and said gate of said sync transistor is electrically coupled to a sync gate carrier segment;
a control transistor having a source and a gate on a top surface of said control transistor, and a drain on a bottom surface of said control transistor;
wherein said drain of said control transistor is electrically coupled to a control drain carrier segment, said source of said control transistor is electrically coupled to said drain of said sync transistor and said gate of said control transistor is electrically coupled to a control gate carrier segment;
a power electrode heat spreader that has a contact surface and that is mechanically coupled along said contact surface to said drain of said sync transistor, said sync drain carrier segment and said source of said control transistor.

16. The power semiconductor package of claim 15 , further comprising a gate electrode heat spreader situated over said gate of said control transistor and configured for attachment to a gate electrode conductive carrier segment.

17. The power semiconductor package of claim 15 , further comprising a wire bond coupling said gate of said control transistor to a gate electrode conductive carrier segment.

18. The power semiconductor package of claim 15 , wherein said sync transistor and said control transistor are selected from the group consi

Assignees

• Infineon Technologies Americas Corp
• Infineon Technologies Americas Corp

Inventors

• Cho Eung San

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title