Nonvolatile memory device and sub-block managing method thereof

Patent metadata

Field	Value
Publication number	US-8964481-B2
Application number	US-201314014504-A
Country	US
Kind code	B2
Filing date	Aug 30, 2013
Priority date	Aug 31, 2012
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

A nonvolatile memory device includes a memory block, a row decoder, a voltage generator and control logic. The memory block includes memory cells stacked in a direction intersecting a substrate, the memory block being divided into sub-blocks configured to be erased independently. The row decoder is configured to select the memory block by a sub-block unit. The voltage generator is configured to generate an erase word line voltage to be provided to a first word line of a selected sub-block of the sub-blocks and a cut-off voltage, higher than the erase word line voltage, to be provided to a second word line of the selected sub-block during an erase operation. The control logic is configured to control the row decoder and the voltage generator to perform an erase operation on the selected sub-block.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a memory block including memory cells stacked in a direction intersecting a substrate, the memory block being divided into a plurality of sub-blocks configured to be erased independently;
a row decoder configured to select the memory block by a sub-block unit;
a voltage generator configured to generate an erase word line voltage to be provided to a first word line of a selected sub-block of the plurality of sub-blo…

Assignees

• Oh Eun Chu
• Kong Junjin
• Samsung Electronics Co Ltd

Inventors

• Oh Eun Chu
• Kong Junjin

Classifications

• G11C16/0483 Primary

  Physics · mapped topic

• H01L27/1157

  Electricity · mapped topic

• G11C16/16 Primary

  Physics · mapped topic

• H01L27/11524

  Electricity · mapped topic

• G11C16/3418

  Physics · mapped topic