Nonvolatile memory device, operating method thereof, and memory system including the same
US-2024233827-A1 · Jul 11, 2024 · US
Programming select gate transistors and memory cells using dynamic verify level
US8929142B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8929142-B2 |
| Application number | US-201313759303-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 5, 2013 |
| Priority date | Feb 5, 2013 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with the slower-programming transistors at the conclusion of the programming operation. For programming of memory cells to different target data states, an offset between the initial and final verify levels can be different for each data state. In one approach, the offset is greater for lower target data states. The increases in the dynamic verify voltage can be progressively smaller with each subsequent program-verify iteration of the programming operation. The start of the increase can be adapted to the programming progress or can be at a predetermined program-verify iteration.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for programming transistors in a memory device, comprising: performing each program-verify iteration of a plurality of program-verify iterations, the plurality of program-verify iterations comprise program-verify iterations for a set of transistors which are to be programmed in a programming operation, each transistor initially has a program status which indicates that the transistor is to be programmed, the performing each program-verify iteration…
Assignees
Inventors
Classifications
Physics · mapped topic
- G11C16/3427Primary
Physics · mapped topic
- G11C16/3459Primary
Physics · mapped topic
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US8929142B2 cover?
- Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with t…
- Who is the assignee on this patent?
- Sandisk Technologies Inc
- What technology area does this patent fall under?
- Primary CPC classification G11C16/3427. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).