High speed receivers circuits and methods

Patent metadata

Field	Value
Publication number	US-9614564-B2
Application number	US-201615073943-A
Country	US
Kind code	B2
Filing date	Mar 18, 2016
Priority date	Dec 27, 2012
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

The present invention provides GPA embodiments. In some embodiments, a GPA stage with a negative capacitance unit is provided.

First claim

What is claimed is:

1. An apparatus comprising:
a differential amplifier having a first transistor with a gate terminal to receive a first input signal, and a second transistor with a gate terminal to receive a second input signal;
an offset cancellation circuit coupled to the differential amplifier; and
a negative impedance circuit having a third transistor with a gate terminal coupled to a drain terminal of the first transistor, and a fourth transistor with a gate terminal coupled to the drain terminal of the second transistor.

2. The apparatus of claim 1 , wherein the gate terminal of the third transistor is coupled to the drain terminal of the fourth transistor.

3. The apparatus of claim 2 , wherein the gate terminal of the fourth transistor is coupled to the drain terminal of the third transistor.

4. The apparatus of claim 3 comprises a capacitive device coupled to source terminals of the third and fourth transistors.

5. The apparatus of claim 1 comprises a first resistive device coupled to the first transistor and a supply node.

6. The apparatus of claim 5 comprises a second resistive device coupled to the second transistor and the supply node.

7. The apparatus of claim 1 comprises a current source coupled to at least one of the source terminal of the first or second transistor.

8. An apparatus comprising:
a first stage including a differential amplifier coupled to an offset cancellation circuit;
a second stage coupled to the first stage, the second stage to reduce parasitic capacitance of one or more nodes of the first stage; and
a third stage coupled to the second stage, wherein the third stage includes an amplifier.

9. The apparatus of claim 8 , wherein the second stage includes a negative impedance circuit having cross-coupled transistors and a capacitive element coupled to the cross-coupled transistors, and wherein the negative impedance circuit is coupled to the differential amplifier.

10. The apparatus of claim 9 , wherein the negative impedance circuit includes a current source coupled to the cross-coupled transistors.

11. The apparatus of claim 8 , wherein the differential amplifier is coupled to a resistive element such that the resistive element is coupled to first and second input transistors of the differential amplifier.

12. The apparatus of claim 8 , wherein an output of the differential amplifier is a differential output which is coupled to gate terminals of the cross-coupled transistors of the negative impedance circuit.

13. The apparatus of claim 8 , wherein the differential amplifier and the negative impedance circuit are part of an analog front-end unit of a receiver.

14. A method to improve gain, the method comprising:
receiving a differential input signal by a differential amplifier;
cancelling offset of the differential amplifier; and
reducing parasitic at one or more nodes of the differential amplifier by a negative impedance circuit.

15. The method of claim 14 , wherein the negative impedance circuit includes cross-coupled transistors and a capacitive element coupled to the cross-coupled transistors, wherein the negative impedance circuit is coupled to the differential amplifier.

16. The method of claim 14 comprises amplifying an output of the negative impedance circuit.

17. The method of claim 14 , wherein the differential amplifier and the negative impedance circuit are part of an analog front-end unit of a receiver.

18. The method of claim 14 , wherein the output of the differential amplifier is a differential output which is coupled to gate terminals of the cross-coupled transistors of the negative impedance circuit.

19. The method of claim 14 , wherein the negative impedance circuit includes a current source coupled to the cross-coupled transistors.

20. An apparatus comprising:
a differential amplifier having an offset cancellation circuit;
a negative impedance circuit to reduce parasitic capacitance of one or more nodes of the differential amplifier; and
an amplifier coupled to the negative impedance circuit.

21. The apparatus of claim 20 , wherein the negative impedance circuit includes:
cross-coupled transistors and a capacitive element coupled to the cross-coupled transistors, and wherein the negative impedance circuit is coupled to the differential amplifier; and
a current source coupled to the cross-coupled transistors.

22. The apparatus of claim 20 , wherein the differential amplifier is coupled to a resistive element such that the resistive element is coupled to first and second input transistors of the differential amplifier.

23. The apparatus of claim 20 , wherein an output of the differential amplifier is a differential output which is coupled to gate terminals of the cross-coupled transistors of the negative impedance circuit.

24. A computing platform, comprising:
a first integrated circuit (IC) having a transmitter to send a bit stream;
a transmission media; and
a second IC coupled to the first IC via the transmission media, the second IC from a second IC having a receiver which is to receive the bit stream, wherein the bit stream is to provide a first input signal and a second input signal, and wherein the receiver comprises:
a differential amplifier having an offset cancellation circuit and first and second transistors with corresponding gate terminals to receive the first and second input signals;
a negative impedance circuit to reduce parasitic capacitance of one or more nodes of the differential amplifier; and
an amplifier coupled to the negative impedance circuit.

25. The computing platform of claim 24 , wherein the negative impedance circuit includes cross-coupled transistors and a capacitive element coupled to the cross-coupled transistors, and wherein the negative impedance circuit is coupled to the differential amplifier.

26. The computing platform of claim 24 , wherein the differential amplifier, the negative impedance circuit, and the amplifier are part of an analog front-end unit of the receiver.

Assignees

• Intel Corp

Inventors

• Chang Kevin
• Giaconi Stefano

Classifications

• H04B3/16 Primary

  characterised by the negative-impedance network used · CPC title

• H04L27/01

  Equalisers {(baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005)} · CPC title

• H04L7/0087 Primary

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H03F2203/45081

  the common mode signal being level shifted before using it for controlling or adding · CPC title

• H04L25/03019

  adaptive, i.e. capable of adjustment during data reception · CPC title