High speed receivers circuits and methods

Patent metadata

Field	Value
Publication number	US-10536178-B2
Application number	US-201715477925-A
Country	US
Kind code	B2
Filing date	Apr 3, 2017
Priority date	Dec 27, 2012
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

The present invention provides GPA embodiments. In some embodiments, a GPA stage with a negative capacitance unit is provided.

First claim

What is claimed is:

1. An apparatus comprising:
a termination impedance;
a base line wander corrector (BLWC) coupled to the termination impedance; and
a VGA coupled to the BLWC, the VGA comprising:
an amplifier; and
a negative impedance circuit coupled to the amplifier.

2. The apparatus of claim 1 , wherein the amplifier has a source-degeneration topology to perform waveform conditioning function.

3. The apparatus of claim 1 comprises a data sampler coupled to the VGA.

4. The apparatus of claim 3 comprises a phase sampler coupled to the VGA.

5. The apparatus of claim 4 comprises a first error sampler coupled to the VGA.

6. The apparatus of claim 5 comprises a second error sampler coupled to the VGA.

7. The apparatus of claim 6 comprises a serial to parallel converter coupled to the data sampler, phase sampler, first error sampler, and second error sampler.

8. The apparatus of claim 7 comprises a binning circuitry coupled to the serial to parallel converter.

9. The apparatus of claim 8 , wherein the binning circuitry comprises:
a first counter to count data samples; and
a second counter to count edge samples.

10. The apparatus of claim 1 comprises an offset cancellation circuitry coupled to the amplifier.

11. The apparatus of claim 10 comprises a signal processing circuitry to provide voltage offset cancellation signal to the offset cancellation circuitry.

12. The apparatus of claim 1 , wherein the negative impedance circuit comprises:
cross-coupled transistors; and
a capacitive device coupled to both the cross-coupled transistors.

13. An apparatus comprising:
means for amplifying a differential signal;
means for cancelling offset associated with the means for amplifying; and
means for reducing parasitic capacitance of one or more nodes of the means for amplifying.

14. The apparatus of claim 13 comprises means for AC coupling the differential signal to the means for amplifying.

15. The apparatus of claim 13 comprises means for common mode control coupled to the means for amplifying.

16. The apparatus of claim 13 , wherein the means for amplifying comprises means for controlling equalization.

17. The apparatus of claim 13 comprises means for common mode detection on a previous cascaded gain stage.

18. An apparatus comprising:
a first integrated circuit (IC) having a transmitter to send a bit stream;
a transmission media; and
a second IC coupled to the first IC via the transmission media, wherein the second IC includes a receiver which is to receive the bit stream, and wherein the receiver comprises:
a termination impedance;
a base line wander corrector (BLWC) coupled to the termination impedance; and
a VGA coupled to the BLWC, the VGA comprising:
an amplifier; and
a negative impedance circuit coupled to the amplifier.

19. The apparatus of claim 18 , wherein the BLWC and VGA are part of an analog front-end of the receiver.

20. The apparatus of claim 18 , wherein the negative impedance circuit comprises cross-coupled transistors and a capacitive device coupled to both the cross-coupled transistors.

Assignees

• Intel Corp

Inventors

• Chang Kevin
• Giaconi Stefano

Classifications

• H03F1/48

  of aperiodic amplifiers · CPC title

• H03F3/4521

  Complementary long tailed pairs having parallel inputs and being supplied in parallel · CPC title

• H04B3/16 Primary

  characterised by the negative-impedance network used · CPC title

• H03F3/45094 Primary

  Folded cascode stages · CPC title

• H04L7/0087 Primary

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title