High speed receivers circuits and methods

Patent metadata

Field	Value
Publication number	US-9614697-B2
Application number	US-201514795090-A
Country	US
Kind code	B2
Filing date	Jul 9, 2015
Priority date	Dec 27, 2012
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

The present invention provides GPA embodiments. In some embodiments, a GPA stage with a negative capacitance unit is provided.

First claim

What is claimed is:

1. An apparatus comprising:
a first transistor having a gate to receive a first input signal;
a second transistor having a gate to receive a second input signal;
a first resistive device coupled to the first transistor and a first supply node;
a second resistive device coupled to the second transistor and the first supply node;
a first capacitive device coupled to the first and second transistors;
a third transistor having a gate terminal coupled to the first transistor;
a fourth transistor having a gate terminal coupled to the second transistor and the third transistor, wherein the gate terminal of the third transistor is coupled to the fourth transistor; and
a second capacitive device directly coupled to the third and fourth transistors.

2. The apparatus of claim 1 comprises a first current source coupled to the first and second transistors, and also coupled to a second supply node.

3. The apparatus of claim 2 comprises a second current source coupled to the third transistor.

4. The apparatus of claim 3 comprises a third current source coupled to the fourth transistor.

5. The apparatus of claim 1 , wherein the first and second resistive devices are transistor based transistors.

6. The apparatus of claim 1 , wherein the first and second capacitive devices are transistor based transistors.

7. An apparatus capable of increasing gain, the apparatus comprising:
a differential amplifier coupled to a resistive element and a first capacitive element such that the first capacitive element and the resistive element are coupled to first and second input transistors of the differential amplifier; and
a negative impedance circuit having cross-coupled transistors and a second capacitive element coupled to the cross-coupled transistors, wherein the negative impedance circuit is coupled to the differential amplifier, and wherein the second capacitive element is coupled to at least two transistors of the negative impedance circuit.

8. The apparatus of claim 7 , wherein the differential amplifier includes at least two current sources, wherein at least one of the current sources is coupled to the first capacitive element.

9. The apparatus of claim 7 , wherein the negative impedance circuit includes a current source coupled to the cross-coupled transistors.

10. The apparatus of claim 7 , wherein the negative impedance circuit is to reduce parasitic capacitance at an output of the differential amplifier.

11. The apparatus of claim 10 , wherein the output of the differential amplifier is a differential output which is directly or indirectly coupled to gate terminals of the cross-coupled transistors of the negative impedance circuit.

12. The apparatus of claim 7 comprises an amplifier coupled to an output of the negative impedance circuit.

13. The apparatus of claim 7 , wherein the differential amplifier and the negative impedance circuit are part of an analog front-end unit of a receiver.

14. A computing platform, comprising:
a first integrated circuit (IC) having a transmitter to send a bit stream;
a transmission media; and
a second IC coupled to the first IC via the transmission media, the second IC from a second IC having a receiver which is to receive the bit stream, wherein the bit stream is to provide a first input signal and a second input signal, and wherein the receiver comprises:
a first transistor having a gate to receive a first input signal;
a second transistor having a gate to receive a second input signal;
a first resistive device coupled to the first transistor and a first supply node;
a second resistive device coupled to the second transistor and the first supply node;
a first capacitive device coupled to the first and second transistors;
a third transistor having a gate terminal coupled to the first transistor;
a fourth transistor having a gate terminal coupled to the second transistor and the third transistor, wherein the gate terminal of the third transistor is coupled to the fourth transistor; and
a second capacitive device directly coupled to the third and fourth transistors.

15. The computing platform of claim 14 , wherein the receiver comprises:
a first current source coupled to the first and second transistors, and also coupled to a second supply node;
a second current source coupled to the third transistor; and
a third current source coupled to the fourth transistor.

16. The system of claim 14 , wherein the first and second resistive devices are transistor based transistors.

17. The system of claim 14 , wherein the first and second capacitive devices are transistor based transistors.

18. An apparatus comprising:
a differential amplifier having:
a first transistor having a gate to receive a first input signal;
a second transistor having a gate to receive a second input signal;
a first resistive device coupled to the first transistor and a first supply node;
a second resistive device coupled to the second transistor and the first supply node;
a first capacitive device coupled to the first and second transistors; and

a negative impedance circuit coupled to the differential amplifier, the negative impedance circuit having:
a first transistor having a gate terminal coupled to the first transistor associated with the differential amplifier;
a second transistor having a gate terminal coupled to the second transistor associated with the differential amplifier, and further coupled to the first transistor, wherein the gate terminal of the first transistor is also coupled to the second transistor; and
a second capacitive device coupled to the first and second transistors of the negative impedance circuit.

19. The apparatus of claim 18 comprises an amplifier coupled to an output of the negative impedance circuit.

20. An apparatus comprising:
a differential amplifier to receive a differential input signal, the differential amplifier having a first capacitive device coupled to input transistors of the differential amplifier; and
a negative impedance circuit coupled to the differential amplifier, wherein the negative impedance circuit is to cancel parasitic capacitance at a node of the differential amplifier, and to increase bandwidth of the differential amplifier, and wherein the negative impedance circuit includes a second capacitive element which is coupled to at least two transistors of the negative impedance circuit.

21. The apparatus of claim 20 , wherein the negative impedance circuit has cross-coupled transistors which are the at least two transistors, wherein the second capacitive element is coupled to the cross-coupled transistors.

22. The apparatus of claim 20 comprises a resistive element coupled to one of the input transistor of the differential amplifier.

Assignees

• Intel Corp

Inventors

• Chang Kevin
• Giaconi Stefano

Classifications

• H04L25/03878

  Line equalisers; line build-out devices · CPC title

• H03F1/48

  of aperiodic amplifiers · CPC title

• H03F1/483

  with field-effect transistors · CPC title

• H04L7/0087 Primary

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H04L27/01

  Equalisers {(baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005)} · CPC title