Input path matching in pipelined continuous-time analog-to-digital converters

Patent metadata

Field	Value
Publication number	US-9614510-B2
Application number	US-201615068231-A
Country	US
Kind code	B2
Filing date	Mar 11, 2016
Priority date	Mar 13, 2015
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

First claim

What is claimed is:

1. A method comprising:
comparing magnitude and phase of a coarse resolution signal path of a first stage sub-analog-to-digital converter (sub-ADC) in a pipelined continuous-time analog-to-digital converter (CT ADC) with magnitude and phase of a continuous-time signal path of the pipelined CT ADC to generate a residue magnitude and phase, using the continuous-time signal path comprising an input delay circuit, the residue magnitude and phase generated by a first summing circuit; and
varying a delay value of at least one digital delay circuit for reducing the residue magnitude and phase, the at least one digital delay circuit positioned at an output of the first stage sub-ADC and coupled to each of the first summing circuit and a second summing circuit, the second summing circuit positioned at an output of a second stage sub-ADC, the second stage sub-ADC coupled to an output of the first summing circuit.

2. The method of claim 1 , wherein the input delay circuit is a passive filter network including at least one low-pass filter and at least one all-pass filter, the least one low-pass filter including at least one resistor-capacitor circuit and the at least one all-pass filter including at least one of: at least one resistor-capacitor circuit and at least one resistor-inductor-capacitor circuit.

3. The method of claim 1 , wherein the input delay circuit is at least one of: a digitally controlled delay and a transmission line producing a fixed delay.

4. The method of claim 1 , wherein the input delay circuit is positioned in the continuous-time signal path between an analog input signal of the pipelined CT ADC and the first summing circuit.

5. The method of claim 1 , wherein the delay value of the at least one digital delay circuit is varied for reducing residue magnitude and phase over at least one of: process, temperature, and voltage variations.

6. The method of claim 5 , wherein the at least one digital delay circuit is coupled to the first summing circuit via a sub-digital-to-analog converter, and coupled to the second summing circuit via a digital noise cancellation filter.

7. The method of claim 1 , the pipelined CT ADC is an integrated circuit and is a pipelined continuous-time delta sigma modulator (CT DSM), and the first stage sub-ADC is a first stage sub-delta sigma modulator (sub-DSM) of a plurality of pipelined sub-DSMs.

8. The method of claim 1 , wherein the at least one digital delay circuit comprises two digital delay circuits, the first digital delay circuit coupled to the first summing circuit and the second digital delay circuit coupled to the second summing circuit, the first digital delay circuit configured to have a delay different from a delay of the second digital delay circuit.

9. An apparatus for pipelined continuous-time analog-to-digital converters (CT ADCs) comprising:
an input delay circuit positioned in a continuous-time signal path of the pipelined CT ADC and coupled to a first summing circuit; and
at least one digital delay circuit positioned at an output of a first stage sub-analog-to-digital converter (sub-ADC) of a plurality of pipelined sub-ADCs, the at least one digital delay circuit coupled to each of the first summing circuit and a second summing circuit, the at least one digital delay circuit configured to vary a delay of the at least one digital delay circuit for reducing a residue magnitude and phase, the residue magnitude and phase representing a difference between magnitude and phase of a coarse resolution signal path of the first stage sub-ADC and magnitude and phase of a continuous-time signal path of the pipelined CT ADC, the first summing circuit configured to generate the residue magnitude and phase, the second summing circuit positioned at an output of a second stage sub-ADC, the second stage sub-ADC coupled to an output of the first summing circuit.

10. The apparatus of claim 9 , wherein the input delay circuit is a passive filter network including at least one low-pass filter and at least one all-pass filter, the least one low-pass filter including at least one resistor-capacitor circuit and the at least one all-pass filter including at least one of: at least one resistor-capacitor circuit and at least one resistor-inductor-capacitor circuit.

11. The apparatus of claim 9 , wherein the input delay circuit is at least one of: a digitally controlled delay and a transmission line producing a fixed delay.

12. The apparatus of claim 9 , wherein the at least one digital delay circuit is coupled to the first summing circuit via a sub-digital-to-analog converter, and coupled to the second summing circuit via a digital noise cancellation filter.

13. The apparatus of claim 9 , wherein the pipelined CT ADC is an integrated circuit and is a pipelined continuous-time delta sigma modulator (CT DSM), and the first stage sub-ADC is a first stage sub-delta sigma modulator (sub-DSM) of a plurality of pipelined sub-DSMs.

14. The apparatus of claim 9 , wherein the at least one digital delay circuit comprises two digital delay circuits, the first digital delay circuit coupled to the first summing circuit and the second digital delay circuit coupled to the second summing circuit, the first digital delay circuit configured to have a delay different from a delay of the second digital delay circuit.

15. A pipelined continuous-time analog-to-digital converter (CT ADC) device comprising:
a first stage sub-analog-to-digital converter (sub-ADC) of a plurality of pipelined sub-ADCs, the first stage sub-ADC configured to receive an analog input signal;
a continuous-time signal path configured to receive the analog input signal, the continuous-time input path including an input delay circuit positioned before a first summing circuit; and
at least one digital delay circuit positioned at an output of the first stage sub-ADC, the at least one digital delay circuit coupled to each of the first summing circuit and a second summing circuit, the at least one digital delay circuit configured to vary a delay of the at least one digital delay circuit for reducing a residue magnitude and phase, the residue magnitude and phase representing a difference between magnitude and phase of a coarse resolution signal path of the first stage sub-ADC and magnitude and phase of the continuous-time signal path, the first summing circuit configured to generate the residue magnitude and phase, the second summing circuit positioned at an output of a second stage sub-ADC of the plurality of pipelined sub-ADCs, the second stage sub-ADC coupled to an output of the first summing circuit.

16. The device of claim 15 further comprising:
a digital noise cancellation filter coupled to an output of the at least one digital delay circuit;
a sub-digital-to-analog converter (sub-DAC) coupled to an output of the at least one digital delay circuit;
the first summing circuit further configured to couple to an output of the sub-DAC, the sub-DAC configured to be coupled to the output of the first stage sub-ADC;
the second stage sub-ADC of the plurality of pipelined sub-ADCs coupled to an output of the first summing circuit; and
the second summing circuit further configured to receive an output of the digital noise cancellation filter, the digital noise cancellation filter coupled to the at least one digital delay circuit.

17. The device of claim 15 , wherein the input delay circuit is a passive filter network including at least one low-pass filter and at least one all-pass filter, the least one low-pass filter including at least one resistor-capacitor circuit and the at least one all-pa

Assignees

• Texas Instruments Inc

Inventors

• Srinivasan Venkatesh
• Shi Kun
• Wang Victoria
• Klemmer Nikolaus

Classifications

• H03M3/386

  over the full range of the converter, e.g. for correcting differential non-linearity · CPC title

• H03M1/001

  Analogue/digital/analogue conversion · CPC title

• H03M3/37

  Compensation or reduction of delay or phase error · CPC title

• H03K5/159 Primary

  Applications of delay lines not covered by the preceding subgroups · CPC title

• H03M1/164

  the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence) · CPC title