Contact for semiconductor fabrication

Patent metadata

Field	Value
Publication number	US-2016111430-A1
Application number	US-201414516278-A
Country	US
Kind code	A1
Filing date	Oct 16, 2014
Priority date	Oct 16, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

A semiconductor device includes a substrate, a fin structure on the substrate, the fin structure comprising a doped region, a first gate over the fin structure, the first gate positioned adjacent the doped region, the first gate having a spacer on a first side and having no spacer on a second side between the gate and the doped region, and a conductive plug that contacts the doped region and a top of the gate.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate; a fin structure on the substrate, the fin structure comprising a doped region; a first gate over the fin structure, the first gate positioned adjacent the doped region, the first gate having a spacer on a first side and having no spacer on a second side between the gate and the doped region; and a conductive plug that contacts the doped region and a top of the gate.

2 . The device of claim 1 , wherein the gate comprises a metal replacement gate.

3 . The device of claim 2 , wherein a high-k dielectric layer formed on the second side of the gate is partially removed such that the conductive plug is in direct contact with the second side.

4 . The device of claim 1 , further comprising, a second gate positioned adjacent the doped region opposite the first gate, the second gate having spacers on both sides.

5 . The device of claim 3 , wherein the conductive plug extends to a spacer of the second gate.

6 . The device of claim 3 , wherein the first gate and second gate are pull-up transistors of a Static Random Access Memory (SRAM) cell.

7 . The device of claim 1 , wherein the doped region comprises a doped epitaxial region.

8 . The device of claim 1 , further comprising a silicide layer formed on the doped region between the doped region and the conductive plug.

9 . The device of claim 1 , wherein the first gate is positioned at a longitudinal end of the fin structure.

10 . The device of claim 1 , wherein the fin structure is formed over an N-well in the substrate.

11 . The device of claim 10 , wherein the first gate is an elongated gate that serves as a gate to a pull-up device over the N-well and a pull-down device formed over a P-well in the substrate.

12 . A semiconductor device comprising:
a substrate; a fin structure formed on the substrate, the fin structure comprising a doped region; a first gate on a first side of the doped region, the first gate having sidewall spacers on both sides; a second gate on a second side of the doped region, the second side being opposite the first side, the second gate having spacers on both sides; a self-aligned contact between the first gate and the second gate; and a butt contact that is in direct connection with a top of the first gate and the self-aligned contact.

13 . The device of claim 12 , wherein the butt contact is in direct contact with a top of the self-aligned contact, the top of the self-aligned contact being at a different height than a top of the first gate.

14 . The device of claim 12 , wherein the butt contact is in direct contact with a top of the self-aligned contact, the top of the self-aligned contact being at a different height than a top of the first gate.

15 . The device of claim 12 , wherein the self-aligned contact is in direct contact with spacers from both the first gate and the second gate.

16 . The device of claim 12 , further comprising, a silicide layer between the doped region and the self-aligned contact.

17 . The device of claim 12 , wherein a portion of a high-k dielectric layer between the first gate and the spacers of the first gate is at least partially removed along a sidewall of the first gate.

18 . A method for forming a semiconductor device, the method comprising:
providing a substrate; forming a fin structure on the substrate; forming a dummy gate over the fin structure; forming sidewall spacers on both sides of the dummy gate; forming a doped region within the fin structure, the doped region being formed adjacent the dummy gate; replacing the dummy gate with a gate; removing a spacer from a first side of the gate, the first side being between the gate and the doped region; and forming a conductive plug that contacts the doped region, the first side of the gate, and a top of the gate.

19 . The method of claim 18 , further comprising, removing a portion of a high-k dielectric layer formed between the gate and the spacers such that the conductive plug makes direct contact with a portion of a sidewall of the gate.

20 . The method of claim 18 , further comprising, forming a second gate adjacent the doped region opposite the first gate, the second gate comprising spacers on both sides, wherein the conductive plug extends to a sidewall spacer of the second gate.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Liaw Jhon Jhy

Classifications

• H10W20/0698 Primary

  Local interconnections · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title