Semiconductor device with strained layer

Patent metadata

Field	Value
Publication number	US-9368626-B2
Application number	US-201314097058-A
Country	US
Kind code	B2
Filing date	Dec 4, 2013
Priority date	Dec 4, 2013
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

A semiconductor device and method of fabricating thereof is described that includes a substrate including at least one fin, at least one gate stack formed on a top surface of the at least one fin, a first inter-layer dielectric (ILD) layer formed on the top surface of the at least one fin, and a strained layer formed at least on a top surface of the at least one gate stack, wherein the strained layer is configured to provide a strain force to the at least one gate stack.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including at least one fin;
at least one gate stack formed on a top surface of the at least one fin;
a first inter-layer dielectric (ILD) layer formed on the top surface of the at least one fin;
a strained insulating layer formed at least on and contacting a top surface of the at least one gate stack and a top surface of the first ILD layer, wherein the first ILD extends along and contacts a sidewall of the at least one fin, and wherein the first ILD further extends from a bottom surface of the strained insulating layer to a top surface of the substrate lower than the top surface of the at least one fin, wherein the strained insulating layer comprises germanium oxide; and
a second ILD layer formed over the strained insulating layer,
wherein the strained insulating layer is configured to provide a strain force to at least one channel region in the at least one fin underlying the at least one gate stack, respectively, and wherein the strained insulating layer is transformed from a pre-strained layer by a treatment through the second ILD layer.

2. The semiconductor device of claim 1 , wherein the strained insulating layer is configured to provide a strain force to the at least one gate stack in a direction perpendicular to the top surface of the at least one fin.

3. The semiconductor device of claim 1 , further comprising at least one source/drain region disposed in the at least one fin.

4. The semiconductor device of claim 1 , wherein the at least one gate stack includes a gate dielectric material and a gate electrode layer.

5. A method of semiconductor fabrication, comprising:
providing a semiconductor substrate;
forming at least one fin in the semiconductor substrate;
forming a plurality of gate stacks over the at least one fin;
forming a first inter-layer dielectric (ILD) layer over the semiconductor substrate, wherein forming the first ILD layer comprises completely filling spaces between adjacent ones of the plurality of gate stacks;
forming a pre-strained layer over top surfaces of the plurality of gate stacks and the first ILD layer, the pre-stained layer being a semiconductor layer;
forming a second ILD layer over the pre-strained layer; and
treating the pre-strained layer through the second ILD layer such that the pre-strained layer is transformed to be a strained layer; the strained layer being on the top surfaces of the plurality of gate stacks and the first ILD layer;
wherein the strained layer is configured to provide a strain force to the plurality of gate stacks.

6. The method of claim 5 , wherein the strained layer is configured to provide a strain force to the plurality of gate stacks in a direction perpendicular to the top surface of the at least one fin.

7. The method of claim 5 , wherein the pre-strained layer includes at least one of silicon and germanium.

8. The method of claim 7 , wherein the strained layer includes at least one of silicon oxide and germanium oxide.

9. The method of claim 8 , wherein the step of treating further includes treating the pre-strained layer with hydrogen peroxide by providing the hydrogen peroxide over the second ILD layer.

10. The method of claim 5 , wherein the plurality of gate stacks is formed after the first ILD layer is formed.

11. The method of claim 10 , wherein the step of forming the plurality of gate stacks further includes:
forming a plurality of polysilicon stacks over the semiconductor substrate;
polishing the plurality of polysilicon stacks and the first ILD layer, after the first ILD layer is formed;
removing the plurality of polysilicon stacks to form at least one trench; and
forming the plurality of gate stacks within the at least one trench.

12. The method of claim 5 , wherein the plurality of gate stacks is formed before the first ILD layer is formed.

13. The method of claim 5 , further comprising:
forming a shallow trench isolation (STI) layer over the semiconductor substrate.

14. The method of claim 5 , further comprising:
forming at least one source/drain region over the semiconductor substrate.

15. The method of claim 14 , wherein the at least one source/drain region is formed by epitaxy process.

16. The method of claim 5 , wherein the step of forming the plurality of gate stacks includes:
forming a gate dielectric material; and
forming a gate electrode layer.

17. The semiconductor device of claim 1 , wherein a top surface of the strained insulating layer is substantially level.

18. The method of claim 5 , wherein the strained layer comprises germanium oxide.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chang Lun-Wei
• Sun yun-ju
• Yamamoto Tomonari

Classifications

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/792

  comprising applied insulating layers, e.g. stress liners · CPC title