Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Carrier and a method for processing a carrier
US9613878B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9613878-B2 |
| Application number | US-201314098570-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 6, 2013 |
| Priority date | Dec 6, 2013 |
| Publication date | Apr 4, 2017 |
| Grant date | Apr 4, 2017 |
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- Title
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- Abstract
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- Assignees and inventors
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- First independent claim
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Abstract
Official abstract text for this publication.
According to various embodiments, a carrier may be provided, the carrier including: a hollow chamber spaced apart from a surface of the carrier; a trench structure extending from the surface of the carrier to the hollow chamber and laterally surrounding a first region of the carrier, the trench structure including one or more trenches extending from the surface of the carrier to the hollow chamber, and one or more support structures intersecting the one or more trenches and connecting the first region of the carrier with a second region of the carrier outside the trench structure, wherein the one or more support structures including an electrically insulating material.
First claim
Opening claim text (preview).
What is claimed is: 1. A carrier comprising: a hollow chamber spaced apart from a surface of the carrier; a trench structure extending from the surface of the carrier to the hollow chamber and laterally surrounding a first region of the carrier, the trench structure comprising one or more trenches extending from the surface of the carrier to the hollow chamber, and one or more support structures intersecting the one or more trenches and connecting the first region of the carrier with a second region of the carrier outside the trench structure, wherein the one or more support structures comprise an electrically insulating material; and a second electronic circuit at least one of over and in the second region of the carrier outside the trench structure, further comprising a first electronic circuit at least one of over and in the first region of the carrier, wherein the first electronic circuit is separate from the second electronic circuit. 2. The carrier according to claim 1 , wherein the electrically insulating material comprises an oxide. 3. The carrier according to claim 1 , wherein the one or more support structures extend laterally between the first region of the carrier and the second region of the carrier. 4. The carrier according to claim 1 , wherein the carrier is a semiconductor carrier. 5. The carrier according to claim 1 , wherein the carrier comprises silicon, and wherein the one or more support structures comprising silicon oxide. 6. The carrier according to claim 1 , wherein the first region of the carrier is electrically isolated from the rest of the carrier via the one or more trenches, the one or more support structures, and the hollow chamber. 7. The carrier according to claim 1 , wherein the hollow chamber is free of solid material. 8. The carrier according to claim 1 , wherein the one or more trenches are free of solid material.
Assignees
Inventors
Classifications
Subject matter not provided for in other groups of this subclass · CPC title
Insulating materials, e.g. resins, glasses or ceramics · CPC title
Containers comprising an insulating or insulated base · CPC title
Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title
- H10W70/68Primary
Shapes or dispositions thereof · CPC title
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9613878B2 cover?
- According to various embodiments, a carrier may be provided, the carrier including: a hollow chamber spaced apart from a surface of the carrier; a trench structure extending from the surface of the carrier to the hollow chamber and laterally surrounding a first region of the carrier, the trench structure including one or more trenches extending from the surface of the carrier to the hollow cham…
- Who is the assignee on this patent?
- Infineon Technologies Dresden Gmbh
- What technology area does this patent fall under?
- Primary CPC classification H10W70/68. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 04 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).