Semiconductor packages and methods for forming semiconductor package

Patent metadata

Field	Value
Publication number	US-9613877-B2
Application number	US-201314051417-A
Country	US
Kind code	B2
Filing date	Oct 10, 2013
Priority date	Oct 10, 2013
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

Semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region on a first surface thereof. The package includes a die having a sensing element. The die is disposed in the die region and is electrically coupled to contact pads disposed on the first surface of the package substrate by insulated wire bonds. A cap is disposed over the first surface of the package substrate. The cap and the first surface of the package substrate define an inner cavity which accommodates the die and the insulated wire bonds. The insulated wire bonds are directly exposed to an environment through at least one access port of the package.

First claim

What is claimed is:

1. A method for forming a semiconductor package comprising:
providing a package substrate, wherein the package substrate comprises first and second major surfaces and a die region on the first surface thereof;
processing the first surface of the substrate, wherein the processed first surface of the substrate comprises protruded portions corresponding to conductive traces and a plurality of recesses between the conductive traces;
processing the second surface of the substrate to form via contacts and a plurality of recesses between the via contacts;
providing a stiffener at least at non-die region of the package substrate, wherein the stiffener is provided below and in direct contact with the conductive traces which are directly coupled to and in direct contact with contact pads disposed on the first surface of the package substrate;
providing a first dielectric layer and filling the recesses between the conductive traces with the first dielectric layer, wherein the first dielectric layer isolates the conductive traces;
providing a second dielectric layer and filling the recesses between the via contacts with the second dielectric layer, wherein the second dielectric layer isolates the via contacts;
providing a die having a sensing element;
attaching the die on the die region;
electrically coupling the die to the contact pads that are disposed on the first surface of the package substrate and are directly coupled to the conductive traces by insulated wire bonds; and
providing a cap over the first surface of the package substrate, wherein the cap and the first surface of the package substrate define an inner cavity which accommodates the die and the insulated wire bonds, and wherein
the insulated wire bond comprises first and second ends, wherein the first end is bonded to die pad of the die while the second end is bonded to the contact pad,
the insulated wire bond comprises a conductive wire and an outer coating surrounding the conductive wire, wherein the outer insulator coating covers and extends to about the entire length of the conductive wire except at portions which are bonded to the die pad and contact pad, and
the insulated wire bonds are directly exposed to an environment through at least one access port of the package.

2. The method of claim 1 wherein:
the cap comprises a top portion and sidewalls; and
the access port extends through inner and outer surfaces of the top portion of the cap.

3. The method of claim 1 wherein:
attaching the die is performed after providing a second dielectric layer.

4. The method of claim 1 wherein:
attaching the die is performed prior to processing the second surface of the substrate.

5. The method of claim 4 comprising:
wherein the second dielectric layer is provided after providing the stiffener.

6. The method of claim 5 wherein:
the stiffener partially extends to the die region of the package substrate; and
the stiffener is provided after processing the second surface of the substrate and prior to providing the second dielectric layer.

7. The method of claim 1 wherein the first and second dielectric layers are separate dielectric layers.

8. The method of claim 1 wherein the package substrate comprises a printed circuit board, metallic, ceramic, semiconductor or leadframe based substrate.

9. The method of claim 1 wherein the first end of the wire bond is bonded to die pad of the die so as to form a ball bond while the second end of the wire bond is bonded to the contact pad so as to form a stitch bond.

10. The method of claim 9 comprising providing protective layers to cover the ball bond and the stitch bond.

11. The method of claim 1 wherein the first end of the wire bond comprises a ball which is electrically coupled to the contact pad and the second end of the wire bond is bonded to a stud bump which is over the die pad so as to form a stitch bond.

12. The method of claim 11 comprising providing protective layers to cover the stud bump and the ball bond.

13. The method of claim 1 comprising providing a surface mount device over the first surface of the package substrate and wherein the wire bond comprises a loop profile having a lateral curvature.

14. The method of claim 1 wherein the cap comprises a top portion and sidewalls, wherein the top portion and sidewalls of the cap are made of different materials.

15. The method of claim 1 wherein:
the cap comprises a top portion and sidewall; and
the access port extends through inner and outer surfaces of the sidewall of the cap.

16. The method of claim 15 comprising providing a sealing ring surrounding the sensing element and providing a lid over a top surface of the sealing ring.

17. The method of claim 1 wherein the access port passes through the first and second surfaces of the package substrate.

18. The method of claim 17 wherein:
the die has a recess which extends from an inactive surface of the die; and
the sensing element is disposed at the bottom of the recess.

Assignees

• United Test And Assembly Center Ltd
• Utac Headquarters Pte Ltd

Inventors

• Suthiwongsunthorn Nathapong
• Beleran John Ducyao
• Pedron Jr Serafin Padilla

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/5525

  comprising copper [Cu] · CPC title