Methods for evaluating semiconductor device structures

Patent metadata

Field	Value
Publication number	US-9613874-B1
Application number	US-201514985178-A
Country	US
Kind code	B1
Filing date	Dec 30, 2015
Priority date	Dec 30, 2015
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

Methods for evaluating semiconductor device structures are provided. In one example, a method includes forming a support layer on a first side of a lamellar sample portion of the semiconductor device structure. The lamellar sample portion has a second side opposite the first side, a target analysis area on or proximate the first side, and a first thickness defined from the first side to the second side. The second side is milled to form a reduced thickness lamellar-supported sample portion that has a milled second side opposite the first side. The support layer is removed from the reduced thickness lamellar-supported sample portion to form a reduced thickness lamellar sample portion having a second thickness that is defined from the first side to the milled second side and that is less than the first thickness. The target analysis area of the reduced thickness lamellar sample portion is evaluated.

First claim

What is claimed is:

1. A method for evaluating a semiconductor device structure, the method comprising:
forming a support layer on a first side of a lamellar sample portion of the semiconductor device structure, wherein the lamellar sample portion has a second side opposite the first side, a target analysis area on or proximate the first side, and a first thickness defined from the first side to the second side, wherein forming the support layer comprises forming the support layer using a technique chosen from a physical vapor deposition (PVD) process or an electron beam gas-injection process;
milling the second side to form a reduced thickness lamellar-supported sample portion that has a milled second side opposite the first side;
removing the support layer from the reduced thickness lamellar-supported sample portion to form a reduced thickness lamellar sample portion having a second thickness that is defined from the first side to the milled second side and that is less than the first thickness; and
evaluating the target analysis area of the reduced thickness lamellar sample portion.

2. The method of claim 1 , wherein forming the support layer comprises forming the support layer on the first side covering the target analysis area.

3. The method of claim 1 , wherein forming the support layer comprises using the electron beam gas-injection process at operating conditions effective to form the support layer.

4. The method of claim 3 , wherein forming the support layer comprises providing a carbon-containing precursor gas to the electron beam gas-injection process.

5. The method of claim 3 , wherein forming the support layer comprises using the electron beam gas-injection process at the operating conditions that include a voltage of from about 1 to about 5 KeV.

6. The method of claim 3 , wherein forming the support layer comprises using the electron beam gas-injection process at the operating conditions that include a current of from about 1.6 to about 3.2 nano-amperes.

7. The method of claim 3 , wherein forming the support layer comprises using the electron beam gas-injection process at the operating conditions that include a deposition time of from about 8 to about 12 minutes.

8. The method of claim 3 , wherein forming the support layer comprises forming the support layer having a layer thickness of from about 150 to about 250 nm.

9. The method of claim 3 , wherein forming the support layer comprises forming the support layer having a length and, independently, a width of from about 200 to about 500 nm.

10. A method for evaluating a semiconductor device structure, the method comprising:
forming a support layer on a first side of a lamellar sample portion of the semiconductor device structure, wherein the lamellar sample portion has a second side opposite the first side, a target analysis area on or proximate the first side, and a first thickness defined from the first side to the second side;
milling the second side to form a reduced thickness lamellar-supported sample portion that has a milled second side opposite the first side;
removing the support layer from the reduced thickness lamellar-supported sample portion to form a reduced thickness lamellar sample portion having a second thickness that is defined from the first side to the milled second side and that is less than the first thickness, wherein removing the support layer comprises removing the support layer using a plasma etching/cleaning process; and
evaluating the target analysis area of the reduced thickness lamellar sample portion.

11. The method of claim 10 , wherein removing the support layer comprises providing oxygen and argon to the plasma etching/cleaning process to remove the support layer.

12. A method for evaluating a semiconductor device structure, the method comprising:
milling at least a portion of the semiconductor device structure to form a lamellar sample portion of the semiconductor device structure, wherein the lamellar sample portion has a first side, a second side opposite the first side, a target analysis area on or proximate the first side, and a first thickness defined from the first side to the second side;
depositing carbon on the first side of the lamellar sample portion to form a support layer on the first side;
milling the second side to form a reduced thickness lamellar-supported sample portion that has a milled second side opposite the first side;
etching the support layer from the reduced thickness lamellar-supported sample portion to form a reduced thickness lamellar sample portion having a second thickness that is defined from the first side to the milled second side and that is less than the first thickness; and
evaluating the target analysis area of the reduced thickness lamellar sample portion.

13. The method of claim 12 , wherein milling the at least the portion of the semiconductor device structure comprises forming the lamellar sample portion having the first thickness of from about 400 to about 600 nm.

14. The method of claim 13 , wherein milling the at least the portion of the semiconductor device structure comprises forming the lamellar sample portion using a focus ion beam (FIB) milling process.

15. The method of claim 12 , wherein milling the second side comprises forming the reduced thickness lamellar-supported sample portion having the second thickness of about 30 nm or less.

16. The method of claim 12 , wherein milling the second side comprises forming the reduced thickness lamellar-supported sample portion using a focus ion beam (FIB) milling process.

17. The method of claim 12 , wherein milling the second side comprises removing at least about 370 nm thickness of material from the second side of the lamellar sample portion to forming the reduced thickness lamellar-supported sample portion.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Zhu Jie
• Liu Binghai
• Er Eddie
• Zhao Si Ping
• Lam Jeffrey

Classifications

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• G01N2223/418

  electron microscope · CPC title

• H01J37/26

  Electron or ion microscopes; Electron or ion diffraction tubes · CPC title

• G01N23/2251

  using incident electron beams, e.g. scanning electron microscopy [SEM] · CPC title

• G01N1/2813

  Producing thin layers of samples on a substrate, e.g. smearing, spinning-on (G01N1/30 takes precedence) · CPC title