Method for simultaneous structuring and chip singulation

Patent metadata

Field	Value
Publication number	US-9610543-B2
Application number	US-201414170187-A
Country	US
Kind code	B2
Filing date	Jan 31, 2014
Priority date	Jan 31, 2014
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A method for structuring a substrate and a structured substrate are disclosed. In an embodiment a method includes providing a substrate with a first main surface and a second main surface, wherein the substrate is fixed to a carrier arrangement at the second main surface, performing a photolithography step at the first main surface of the substrate to mark a plurality of sites at the first main surface, the plurality of sites corresponding to future perforation structures and future kerf regions for a plurality of future individual semiconductor chips to be obtained from the substrate, and plasma etching the substrate at the plurality of sites until the carrier arrangement is reached, thus creating the perforation structures within the plurality of individual semiconductor chips and simultaneously separating the individual semiconductor chips along the kerf regions.

First claim

What is claimed is:

1. A method comprising:
providing a substrate with a first main surface and a second main surface, wherein the substrate is fixed to a carrier arrangement at the second main surface;
performing a photolithography step at the first main surface of the substrate to mark a plurality of sites at the first main surface, the plurality of sites corresponding to future perforation structures and future kerf regions for a plurality of future individual semiconductor chips to be obtained from the substrate, wherein the plurality of individual semiconductor chips comprises at least one of membrane filters, sieves, grids, hole plates, and pressure impulse attenuators; and
plasma etching the substrate at the plurality of sites until the carrier arrangement is reached, thus creating the perforation structures within the plurality of individual semiconductor chips and simultaneously separating the individual semiconductor chips along the kerf regions.

2. The method according to claim 1 , wherein the carrier arrangement comprises a glass carrier and a glue layer.

3. The method according to claim 1 , further comprising thinning the substrate at the first main surface prior to performing the photolithography step.

4. The method according to claim 1 , further comprising:
adhering the plurality of separated semiconductor chips to a tape at their first surfaces after the plasma etching; and
removing the carrier arrangement.

5. The method according to claim 1 , wherein the plasma etching comprises at least one of a deep reactive ion etching dry etch process and a Bosch process.

6. The method according to claim 1 , wherein the carrier arrangement serves as an etch stop for the plasma etching.

7. The method according to claim 1 , wherein at least one of the plurality of individual semiconductor chips is bounded by a non-rectangular kerf region.

8. The method according to claim 1 , wherein the perforation structure comprises a plurality of through-holes through the substrate arranged in a circumferential pattern around an unperforated region of each semiconductor chip.

9. The method according to claim 1 , wherein at least one of the semiconductor chips forms a pressure attenuating hole plate for a microphone, wherein the perforation structure comprises at least one through-hole located at a position aligned with a suspension arrangement of a membrane of the microphone.

10. The method according to claim 1 , wherein the substrate has a thickness less than 100 μm when the plasma etching starts.

11. The method according to claim 1 , wherein a maximal mechanical stress within the substrate of the plurality of individual semiconductor chips after the plasma etching is less than 50 MPa.

12. A method comprising:
providing a substrate with a first main surface and a second main surface, wherein the substrate is fixed to a carrier arrangement at the second main surface;
thinning the substrate at the first main surface;
performing, after thinning, a photolithography step at the first main surface of the substrate to mark a plurality of sites at the first main surface, the plurality of sites corresponding to future perforation structures and future kerf regions for a plurality of future individual semiconductor chips to be obtained from the substrate; and
plasma etching the substrate at the plurality of sites until the carrier arrangement is reached, thus creating the perforation structures within the plurality of individual semiconductor chips and simultaneously separating the individual semiconductor chips along the kerf regions.

13. A method comprising:
providing a substrate with a first main surface and a second main surface, wherein the substrate is fixed to a carrier arrangement at the second main surface;
performing a photolithography step at the first main surface of the substrate to mark a plurality of sites at the first main surface, the plurality of sites corresponding to future perforation structures and future kerf regions for a plurality of future individual semiconductor chips to be obtained from the substrate; and
plasma etching the substrate at the plurality of sites until the carrier arrangement is reached, thus creating the perforation structures within the plurality of individual semiconductor chips and simultaneously separating the individual semiconductor chips along the kerf regions, wherein at least one of the semiconductor chips forms a pressure attenuating hole plate for a microphone, wherein the perforation structure comprises at least one through-hole located at a position aligned with a suspension arrangement of a membrane of the microphone.

14. A method comprising:
providing a glass substrate with a first main surface and a second main surface, wherein the glass substrate is fixed to a carrier arrangement at the second main surface;
performing a photolithography step at the first main surface of the glass substrate to mark a plurality of sites at the first main surface, the plurality of sites corresponding to future perforation structures and future kerf regions for a plurality of future individual chips to be obtained from the glass substrate; and
plasma etching the glass substrate at the plurality of sites until the carrier arrangement is reached, thus creating the perforation structures within the plurality of individual chips and simultaneously separating the individual chips along the kerf regions.

15. The method according to claim 14 , wherein the plurality of individual chips comprise at least one of membrane filters, sieves, grids, hole plates, and pressure impulse attenuators.

16. The method according to claim 14 , wherein the carrier arrangement comprises a glass carrier and a glue layer.

17. The method according to claim 14 , wherein at least one of the chips forms a pressure attenuating hole plate for a microphone, wherein the perforation structure comprises at least one through-hole located at a position aligned with a suspension arrangement of a membrane of the microphone.

Assignees

• Infineon Technologies Ag

Inventors

• Grille Thomas
• Hedenig Ursula
• Roesner Michael
• Stranzl Gudrun
• Zgaga Martin

Classifications

• B81B2201/0257

  Microphones or microspeakers · CPC title

• Y10T428/24273

  including aperture · CPC title

• B81B2201/10

  Microfilters, e.g. for gas or fluids · CPC title

• B01D67/0034 Primary

  by micromachining techniques, e.g. using masking and etching steps, photolithography · CPC title

• B81C1/00904 Primary

  Multistep processes for the separation of wafers into individual elements not provided for in groups B81C1/00873 - B81C1/00896 · CPC title