Package substrate comprising surface interconnect and cavity comprising electroless fill

Patent metadata

Field	Value
Publication number	US-9609751-B2
Application number	US-201414251486-A
Country	US
Kind code	B2
Filing date	Apr 11, 2014
Priority date	Apr 11, 2014
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a first electroless metal layer. The first dielectric layer includes a first surface and a second surface. The first interconnect is on the first surface of the substrate layer. The first cavity traverses the first surface of the first dielectric layer. The first electroless metal layer is formed at least partially in the first cavity. The first electroless metal layer defines a second interconnect embedded in the first dielectric layer. In some implementations, the substrate further includes a core layer. The core layer includes a first surface and a second surface. The first surface of the core layer is coupled to the second surface of the first dielectric layer. In some implementations, the substrate further includes a second dielectric layer.

First claim

What is claimed is:

1. A substrate comprising:
a first dielectric layer comprising a first surface and a second surface;
a first interconnect on the first surface of the first dielectric layer, wherein the first interconnect has a first metal layer and a second metal layer over the first metal layer, wherein the second metal layer is thicker than the first metal layer; and
a second interconnect embedded in a first trench in the first surface of the first dielectric layer, the first trench is at least partially filled with the first metal layer and has an absence of the second metal layer over the first metal layer.

2. The substrate of claim 1 , further comprising:
a first pad on the first surface of the first dielectric layer;
a first via traversing the first dielectric layer, the first via coupled to the first pad; and
a second pad embedded in the first dielectric layer, the second pad embedded through the second surface of the first dielectric layer, wherein the second pad is coupled to the first via.

3. The substrate of claim 1 , further comprising a core layer comprising a first surface and a second surface, wherein the first surface of the core layer is coupled to the second surface of the first dielectric layer.

4. The substrate of claim 3 , wherein the core layer comprises a first via, and the first via includes a first metal layer and a second metal layer over the first metal layer and further wherein the first metal layer is formed on sidewalls of the first via.

5. The substrate of claim 3 , further comprising a second dielectric layer comprising a first surface and a second surface, wherein the first surface of the second dielectric layer is coupled to the second surface of the core layer.

6. The substrate of claim 1 , further comprising:
a first pad on the first surface of the first dielectric layer, the first pad coupled to the second interconnect.

7. The substrate of claim 1 , wherein the substrate is one of at least a package substrate and/or an interposer.

8. The substrate of claim 1 , wherein the substrate is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

9. The substrate of claim 1 , wherein the first metal layer is a seed layer and is distinct from the second metal layer.

10. The substrate of claim 1 , wherein the first metal layer is an electroless fill layer and is distinct from the second metal layer.

11. The substrate of claim 1 , wherein the first metal layer includes a distinct metal composition than the second metal layer.

12. The substrate of claim 1 , wherein the first interconnect is in contact with and above the first surface of the first dielectric layer.

13. The substrate of claim 1 , wherein the second interconnect is fully below the first surface of the first dielectric layer.

14. The substrate of claim 1 , wherein the first interconnect and the second interconnect are traces, and the second interconnect is narrower than the first interconnect.

15. A substrate comprising:
a first dielectric layer comprising a first surface and a second surface;
a first interconnect on the first surface of the first dielectric layer, wherein the first interconnect has an electroless metal layer and an electrolytic metal layer over the electroless metal layer; and
a second interconnect embedded in a first trench in the first surface of the first dielectric layer, the first trench is at least partially filled with the electroless metal layer and has an absence of the electrolytic metal layer over the electroless metal layer; and
further comprising a resist layer on the first dielectric layer, in the first trench, and over the electroless metal layer.

16. A substrate comprising:
a first dielectric layer comprising a first surface and a second surface;
a first interconnect on the first surface of the first dielectric layer, wherein the first interconnect has an electroless metal layer and an electrolytic metal layer over the electroless metal layer; and
a second interconnect embedded in a first trench in the first surface of the first dielectric layer, the first trench is at least partially filled with the electroless metal layer and has an absence of the electrolytic metal layer over the electroless metal layer; further comprising:
a third interconnect, adjacent to the second interconnect and embedded in a second trench in the first surface of the first dielectric layer, the second trench is at least partially filled with the electroless metal layer and has an absence of the electrolytic metal layer over the electroless metal layer, wherein a spacing between the second interconnect and the third interconnect is 3 microns (μm) or less.

Assignees

• Qualcomm Inc

Inventors

• Jomaa Houssam Wafic
• Bchir Omar James
• Kim Chin-Kwan

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/685 Primary

  comprising multiple insulating layers · CPC title

• H05K1/0298

  Multilayer circuits · CPC title