Semiconductor device having trench capacitor structure integrated therein

Patent metadata

Field	Value
Publication number	US-9608130-B2
Application number	US-201213716381-A
Country	US
Kind code	B2
Filing date	Dec 17, 2012
Priority date	Dec 27, 2011
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate. The substrate includes multiple capacitor regions, such as a first capacitor region and a second capacitor region that are adjacent to one another. Each capacitor region includes trenches that are formed within the substrate. A metal-insulator-metal capacitor is formed within the trenches and at least partially over the substrate. The trenches disposed within the first capacitor region are at least substantially perpendicular to the trenches disposed within the second capacitor region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate including a diffusion region;
a plurality of capacitor regions disposed within the diffusion region of the substrate, each capacitor region including a plurality of trenches disposed therein; and
a metal-insulator-metal (MIM) capacitor formed within the plurality of trenches of a first capacitor region, the metal-insulator-metal (MIM) capacitor defining a seam to facilitate stress management,
wherein the plurality of trenches disposed within the first capacitor region of the plurality of capacitor regions are at least substantially perpendicular to the plurality of trenches disposed within a second capacitor region of the plurality of capacitor regions, the second capacitor region adjacent to the first capacitor region, respective trenches of the plurality of trenches having an aspect ratio ranging from about one hundred and twenty-five to one (125:1) to about one hundred and fifty to one (150:1), the metal-insulator-metal capacitor comprising a capacitive density ranging from three hundred femtoFarads per square micrometer (300 fF/um 2 ) to two thousand femtoFarads per square micrometer (2,000 fF/um 2 ), the metal-insulator-metal capacitor including a plurality of dielectric layers, the plurality of dielectric layers comprising alternating layers of Hafnium(IV) oxide and aluminum oxide, wherein a ratio of Hafnium(IV) oxide to aluminum oxide ranges from one and a half (1.5) to two and a half (2.5).

2. The semiconductor device as recited in claim 1 , wherein at least trench of the plurality of trenches includes at least one of a chamfered or rounded corner for facilitating stress management.

3. The semiconductor device as recited in claim 1 , wherein the metal-insulator-metal capacitor comprises a unit cell having a specific x and y stepping layout that results in overlapping of the peripheral contacts, wherein one or more contacts are maintained at a boundary of an internal unit cell to reduce resistance.

4. The semiconductor device as recited in claim 1 , further comprising a plurality of contacts is electrically connected with the metal-insulator-metal capacitor, wherein at least one contact of the plurality of contacts is elongated and redundant with respect to another contact of the plurality of contacts to reduce resistance.

5. The semiconductor device as recited in claim 4 , further comprising at least substantially parallel metal layers to reduce resistance, wherein the plurality of contacts are arranged in an interdigitated configuration, wherein each contact of the plurality of contacts is electrically connected to at least one metal layer of the at least substantially parallel metal layers.

6. A semiconductor device comprising:
a substrate including a diffusion region;
a plurality of capacitor regions disposed within the diffusion region of the substrate, each capacitor region including a plurality of trenches disposed therein; and
a dual metal-insulator-metal (MIM) capacitor formed within the plurality of trenches of a first capacitor region of the plurality of capacitor regions, the dual metal-insulator-metal (MIM) capacitor defining a seam to facilitate stress management,
wherein the plurality of trenches disposed within the first capacitor region of the plurality of capacitor regions are at least substantially perpendicular to the plurality of trenches disposed within a second capacitor region of the plurality of capacitor regions, the second capacitor region adjacent to the first capacitor region, respective trenches of the plurality of trenches having an aspect ratio ranging from about one hundred and twenty-five to one (125:1) to about one hundred and fifty to one (150:1), the dual metal-insulator-metal capacitor comprising a capacitive density ranging from three hundred femtoFarads per square micrometer (300 fF/um 2 ) to two thousand femtoFarads per square micrometer (2,000 fF/um 2 ), the dual metal-insulator-metal capacitor including a plurality of dielectric layers, the plurality of dielectric layers comprising alternating layers of Hafnium(IV) oxide and aluminum oxide, wherein a ratio of Hafnium(IV) oxide to aluminum oxide ranges from one and a half (1.5) to two and a half (2.5).

7. The semiconductor device as recited in claim 6 , wherein at least trench of the plurality of trenches includes at least one of a chamfered or rounded corner for facilitating stress management.

8. The semiconductor device as recited in claim 6 , wherein the metal-insulator-metal capacitor comprises a unit cell having a specific x and y stepping layout that results in overlapping of the peripheral contacts, wherein one or more contacts are maintained at a boundary of an internal unit cell to reduce resistance.

9. The semiconductor device as recited in claim 6 , further comprising a plurality of contacts is electrically connected with the metal-insulator-metal capacitor, wherein at least one contact of the plurality of contacts is elongated and redundant with respect to another contact of the plurality of contacts to reduce resistance.

10. The semiconductor device as recited in claim 9 , further comprising at least substantially parallel metal layers to reduce resistance, wherein the plurality of contacts are arranged in an interdigitated configuration, wherein each contact of the plurality of contacts is electrically connected to at least one metal layer of the at least substantially parallel metal layers.

Assignees

• Maxim Integrated Products

Inventors

• Tran Khanh
• Ellul Joseph P
• Godshalk Edward M
• Ikeuchi Kiyoko
• Srivastava Anuranjan

Classifications

• H01L28/91

  Electricity · mapped topic

• H01L29/66083

  Electricity · mapped topic

• H01L29/92 Primary

  Electricity · mapped topic

• H10D48/021

  of two-electrode devices · CPC title

• H10D1/716

  having vertical extensions · CPC title