Methods of fabricating a semiconductor structure

Patent metadata

Field	Value
Publication number	US-10121849-B2
Application number	US-201514941665-A
Country	US
Kind code	B2
Filing date	Nov 16, 2015
Priority date	Nov 16, 2015
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

A semiconductor structure and a method of fabricating thereof are provided. The method includes the following steps. A substrate with an upper surface and a lower surface is received. A first recess extending from the upper surface to the lower surface is formed and the first recess has a first depth. A second recess extending from the upper surface to the lower surface is formed and the second recess has a second depth less than the first depth. A first conducting layer is formed in the first recess and the second recess. A first insulating layer is formed over the first conducting layer. A second conducting layer is formed over the first insulating layer and isolated from the first conducting layer with the first insulating layer. The substrate is thinned from the lower surface to expose the second conducting layer in the first recess.

First claim

What is claimed is:

1. A method of fabricating a semiconductor structure, comprising:
forming a first recess extending from an upper surface toward a lower surface of a material, the first recess having a first depth;
forming a second recess extending from the upper surface toward the lower surface, the second recess having a second depth less than the first depth;
forming a first insulating layer in the first recess and the second recess;
forming a first conducting layer in the first recess and the second recess and over the first insulating layer;
forming a second insulating layer over the first conducting layer and in the first recess and the second recess;
forming a second conducting layer over the second insulating layer and in the first recess and the second recess, the second conducting layer isolated from the first conducting layer with the second insulating layer;
thinning the material from the lower surface to expose the first insulating layer, the first conducting layer, the second insulating layer, and the second conducting layer in the first recess and the first insulating layer and the first conducting layer in the second recess;
forming a metal layer in direct contact with a portion of the upper surface of the material, with the first insulating layer, the first conducting layer, the second insulating layer, and the second conducting layer in the first recess, and with the second conducting layer in the second recess; and
forming another metal layer in direct contact with a portion of the lower surface of the material, with the first insulating layer, the first conducting layer, the second insulating layer, and the second conducting layer in the first recess, and with the first insulating layer and the first conducting layer in the second recess.

2. The method of claim 1 , wherein forming the first recess and forming the second recess comprises forming the first recess and the second recess by laser drilling, dry etching or wet etching.

3. The method of claim 2 , wherein forming the first recess and forming the second recess comprises forming the first recess and the second recess by reactive ion etching.

4. The method of claim 1 , wherein forming the first recess and forming the second recess comprise:
forming a photoresist layer over the upper surface of the material, the photoresist layer having a first opening and a second opening smaller than the first opening; and
etching the material through the first opening to form the first recess and through the second opening to form the second recess.

5. The method of claim 1 , wherein thinning the material from the lower surface comprises thinning the material by backside grinding, chemical-mechanical polishing or blanket etching.

6. The method of claim 1 , wherein forming the first recess and forming the second recess comprises forming a first dimension of the first recess larger than a second dimension of the second recess.

7. The method of claim 1 , wherein forming the first conducting layer and the second conducting layer comprises forming the first conducting layer and the second conducting layer by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) or plasma-enhanced chemical-vapor deposition (PECVD).

8. The method of claim 1 , wherein forming the first insulating layer and forming the second insulating layer comprises forming the first insulating layer and the second insulating layer by CVD, ALD, PVD or PECVD.

9. The method of claim 1 , wherein thinning the material from the lower surface to expose the first insulating layer, the first conducting layer, the second insulating layer, and the second conducting layer in the first recess comprises forming a via structure comprising the first insulating layer, the first conducting layer, the second insulating layer, and the second conducting layer in the first recess.

10. The method of claim 9 , wherein forming the metal layer in direct contact with a portion of the upper surface of the material comprises forming the metal layer in direct contact with the first insulating layer, the first conducting layer, the second insulating layer, and the second conducting layer of the via structure.

11. The method of claim 1 , wherein thinning the material from the lower surface to expose the first insulating layer, the first conducting layer, the second insulating layer, and the second conducting layer in the first recess and the first insulating layer and the first conducting layer in the second recess comprises forming a capacitor structure comprising the first insulating layer, the first conducting layer, the second insulating layer, and the second conducting layer in the second recess.

12. The method of claim 11 , wherein forming the metal layer in direct contact with a portion of the upper surface of the material comprises forming the metal layer only on the second conducting layer of the capacitor structure.

13. The method of claim 1 , wherein forming the first conducting layer in the first recess and the second recess, forming the second insulating layer over the first conducting layer and in the first recess and the second recess, and forming the second conducting layer over the second insulating layer and in the first recess and the second recess comprises completely filling the first recess and the second recess.

14. A method of fabricating a semiconductor structure, comprising:
forming a first recess in an upper surface of a material, the first recess having a first depth;
forming a second recess in the upper surface of the material, the second recess having a second depth less than the first depth;
forming a first insulating layer in the first recess and the second recess;
forming a first conducting layer in the first recess and the second recess and over the first insulating layer;
forming a second insulating layer over the second conducting layer and in the first recess and the second recess;
forming a second conducting layer over the first insulating layer and in the first recess and the second recess;
thinning the material from a lower surface of the material to expose the first insulating layer, the first conducting layer, the second insulating layer, and the second conducting layer in the first recess and the first insulating layer and the first conducting layer in the second recess;
forming a metal in direct contact with the upper surface of the material and the first conducting layer, the first insulating layer, the second conducting layer, and the second insulating layer in the first recess and in direct contact with only the second conducting layer in the second recess; and
forming another metal in direct contact with the first insulating layer, the first conducting layer, the second insulating layer, and the second conducting layer in the first recess, with the first insulating layer and the first conducting layer in the second recess, and with only a portion of the lower surface of the material.

15. The method of claim 14 , wherein forming the second conducting layer over the first insulating layer and in the first recess and the second recess comprises forming the second conducting layer in the second recess, the second conducting layer isolated from the first conducting layer in the second recess.

Assignees

• Micron Technology Inc

Inventors

• Wu Tieh-Chiang
• Shih Shing-Yih

Classifications

• H10W20/2128

  Coaxial through-semiconductor vias · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10P52/402

  of semiconductor materials · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/242

  of Group IV materials · CPC title