Hybrid active-field gap extended drain MOS transistor

Patent metadata

Field	Value
Publication number	US-9608088-B2
Application number	US-201414284696-A
Country	US
Kind code	B2
Filing date	May 22, 2014
Priority date	Oct 26, 2010
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.

First claim

What is claimed is:

1. A process of forming an integrated circuit, comprising:
forming an extended drain MOS transistor including:
forming an extended drain in a substrate, said extended drain including a drift region with alternating field gap drift regions and active gap regions, and said drift region abuts a channel region of said extended drain MOS transistor;
forming field oxide elements in said extended drain adjacent to said field gap drift regions and opposite from said channel region, such that said extended drain extends below said field oxide elements;
forming a gate dielectric layer on said substrate over said channel region and said drift region;
forming a gate on said gate dielectric layer over said channel region, said gate including field plates over said field gap drift regions and extending onto said field oxide elements; and
forming a drain contact diffused region in said extended drain, the drain contact diffused region having a higher doping concentration than said extended drain, the drain contact diffused region abutting said active gap regions and interleaving with said field oxide elements.

2. The process of claim 1 , in which an active gap width of each said active gap region between adjacent said field plates is less than 2 microns.

3. The process of claim 1 , in which an active gap width of each said active gap region between adjacent said field plates is less than 1 micron.

4. The process of claim 1 , in which said field plates have a tapered shape, so that a drain end width of each said field plate over said field oxide element is at least 100 nanometers less than a source end width of each said field plate on an opposite side of said field plate from said field oxide element.

5. The process of claim 1 , in which said field plates have a retrograde tapered shape, so that a drain end width of each said field plate over said field oxide element is at least 100 nanometers more than a source end width of each said field plate on an opposite side of said field plate from said field oxide element.

6. The process of claim 1 , in which said extended drain MOS transistor is n-channel.

7. The process of claim 1 , in which said extended drain MOS transistor is p-channel.

8. The process of claim 1 , in which said step of forming said field oxide elements is performed with STI processes.

9. The process of claim 1 , in which said step of forming said field oxide elements is performed with LOCOS processes.

10. The process of claim 1 , further comprising:
forming a source in said substrate in said substrate abutting said channel region;
forming a first drain contact on said drain diffused region and adjacent to each said active gap region;
forming a second drain contact on said drain diffused region and adjacent to each said field oxide element opposite one of said field plates and overlapping one of said field oxide elements; and
forming source contacts on said source,
wherein a distance from said source contacts to said second drain contact is more than a distance from said source contacts to said first drain contact.

11. The process of claim 1 , further comprising:
forming a source in said substrate in said substrate abutting said channel region,
wherein said extended drain MOS transistor includes said source, said extended drain and said channel region along a common plane proximate to a top surface of said extended drain MOS transistor.

Assignees

• Texas Instruments Inc

Inventors

• Pendharkar Sameer P
• Lin John

Classifications

• H10P58/00

  Singulating wafers or substrates into multiple chips, i.e. dicing · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H01L29/0696

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic

• H01L29/4238

  Electricity · mapped topic