Method of wafer-scale integration of semiconductor devices and semiconductor device

Patent metadata

Field	Value
Publication number	US-9608035-B2
Application number	US-201314401499-A
Country	US
Kind code	B2
Filing date	Apr 5, 2013
Priority date	May 15, 2012
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

The method of wafer-scale integration of semiconductor devices comprises the steps of providing a semiconductor wafer ( 1 ), a further semiconductor wafer ( 2 ), which differs from the first semiconductor wafer in at least one of diameter, thickness and semiconductor material, and a handling wafer ( 3 ), arranging the further semiconductor wafer on the handling wafer, and bonding the further semiconductor wafer to the semiconductor wafer. The semiconductor device may comprise an electrically conductive contact layer ( 6 ) arranged on the further semiconductor wafer ( 2 ) and a metal layer connecting the contact layer with an integrated circuit.

First claim

The invention claimed is:

1. A method of wafer-scale integration of semiconductor devices, comprising:
providing a semiconductor wafer;
providing a further semiconductor wafer, which differs from the semiconductor wafer in diameter and semiconductor material;
providing a handling wafer;
dividing the further semiconductor wafer by means of wafer dicing;
arranging the further semiconductor wafer on the handling wafer after wafer dicing; and
bonding the further semiconductor wafer to the semiconductor wafer by a bonding layer,
wherein the handling wafer is divided into dies along sawing lines in a subsequent wafer dicing process.

2. The method of claim 1 , wherein
the further semiconductor wafer is cadmium telluride or cadmium zinc telluride.

3. The method of claim 1 or 2 , further comprising:
arranging electrically conductive contact pads between the semiconductor wafer and the further semiconductor wafer; and
arranging an electrically conductive contact layer between the further semiconductor wafer and the handling wafer.

4. The method of claim 3 , further comprising:
forming at least one opening in the semiconductor wafer and/or the further semiconductor wafer, the opening uncovering an area of one of the contact pads and/or the contact layer; and
applying an electrically conductive layer forming a through-wafer contact in the opening on the uncovered area.

5. The method of claim 1 or 2 , wherein
the further semiconductor wafer is thinner than the handling wafer when the further semiconductor wafer is arranged on the handling wafer; and
the handling wafer is afterwards thinned to a remaining cover layer, which is thinner than the further semiconductor wafer.

Assignees

• Ams Ag

Inventors

• Cassidy Cathal
• Siegert Joerg
• Schrank Franz

Classifications

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/30

  Die-attach connectors · CPC title

• H01L24/83

  Electricity · mapped topic

• H01L2924/37001

  Electricity · mapped topic

• H01L2924/14

  Electricity · mapped topic