Method and circuits for communication in multi-die packages

Patent metadata

Field	Value
Publication number	US-9607948-B2
Application number	US-201514674321-A
Country	US
Kind code	B2
Filing date	Mar 31, 2015
Priority date	Mar 31, 2015
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Various example implementations are directed to circuits and methods for inter-die communication on a multi-die integrated circuit (IC) package. According to an example implementation, an IC package includes a first semiconductor die having a plurality of communication circuits for communicating data over respective data terminals of the package. The package also includes a second semiconductor die having N contacts for communicating data to and from the semiconductor die. The second semiconductor die includes a logic circuit configured to communicate M parallel data signals with one or more other semiconductor dies of the package, wherein M>N. The second semiconductor die also includes a plurality of serializer circuits, each configured to serialize data from a respective subset of the plurality of the M signal lines to produce serialized data and provide the serialized data to a respective one of the contacts.

First claim

What is claimed is:

1. An apparatus, comprising:
an interposer;
a first semiconductor die disposed on the interposer;
a second semiconductor die disposed on the interposer;
M signal lines on the first semiconductor die;
a logic circuit on the first semiconductor die, the logic circuit configured to communicate M data signals, via the M signal lines, with the second semiconductor die communicatively coupled to the first semiconductor die;
a plurality of contacts on the first semiconductor die including at least N contacts, wherein the number of N contacts is less than the number of M signal lines and each contact is coupled to the second semiconductor die via a respective signal path; and
a plurality of serializer circuits on the first semiconductor die, each configured to serialize data from a respective subset of the plurality of the M signal lines to produce serialized data and provide the serialized data to a respective one of the contacts;
a deserializer circuit disposed on the second semiconductor die and coupled to receive the serialized data from the first semiconductor die via a respective one of the signal paths, wherein the deserializer circuit is configured to:
deserialize the serialized data to produce a set of parallel data signals; and
provide each data signal of the set of parallel data signals on a respective data terminal.

2. The apparatus of claim 1 , wherein:
the second semiconductor die and the first semiconductor die are disposed in an integrated circuit (IC) package having a set of data terminals for communication of data to and from the IC package; and
the second semiconductor die includes a plurality of communication circuits, each configured to receive a data signal from the deserializer circuit and communicate data via a respective one of the set of data terminals.

3. The apparatus of claim 2 , wherein the first semiconductor die further includes a plurality of deserializer circuits, each configured to receive serialized data from a respective one of the contacts and to produce deserialized data and distribute the deserialized data to a respective plurality of the M signal lines.

4. The IC package of claim 2 , wherein at least one of the plurality of communication circuits of the second semiconductor die is coupled to receive serialized data from a respective one of the signal paths and is configured to transmit the serialized data via the respective one of the set of data terminals.

5. An apparatus, comprising:
an integrated circuit (IC) package having a set of data terminals for communication of data to and from the IC package;
a first semiconductor die disposed in the IC package;
one or more semiconductor dies including a second semiconductor die disposed in the package;
M signal lines on the first semiconductor die;
a logic circuit on the first semiconductor die, the logic circuit configured to communicate M data signals, via the M signal lines, with the one or more semiconductor dies communicatively coupled to the first semiconductor die;
a plurality of contacts on the first semiconductor die including at least N contacts, wherein the number of N contacts is less than the number of M signal lines and each contact is coupled to another one of the one or more semiconductor dies via a respective signal path;
a plurality of serializer circuits on the first semiconductor die, each configured to serialize data from a respective subset of the plurality of the M signal lines to produce serialized data and provide the serialized data to a respective one of the contacts;
wherein the second semiconductor die includes:
a plurality of communication circuits, each configured to communicate data via a respective one of the set of data terminals; and
a deserializer circuit coupled to receive the serialized data from the first semiconductor die via a respective one of the signal paths and configured to:
deserialize the serialized data to produce a set of parallel data signals; and
provide each data signal of the set of parallel data signals to a respective communication circuit of the plurality of communication circuits, wherein the respective communication circuit is configured to transmit the data signal on a respective one of the data terminals.

6. The IC package of claim 2 , wherein at least one communication circuit of the plurality of communication circuits of the second semiconductor die is configured to:
demodulate a signal received from the respective data terminal to produce a demodulated signal including serialized data; and
transmit the demodulated signal to the logic circuit via a respective one of the signal paths.

7. The IC package of claim 2 , wherein:
two or more of the plurality of communication circuits are each configured to demodulate a respective signal received from the respective data terminal to produce a respective demodulated signal; and
the second semiconductor die further includes a serializer circuit configured to serialize the demodulated signals produced by the two or more of the plurality of communication circuits to produce a respective serialized signal and transmit the respective serialized signal to the first semiconductor die via one of the signal paths.

8. The IC package of claim 2 , wherein:
the first semiconductor die includes a plurality of programmable logic resources having a first lithography process size; and
circuits of the second semiconductor die have a second lithography process larger than the first lithography process size.

9. The IC package of claim 2 , further comprising:
a substrate in the IC package; and
an interposer on the substrate and configured to couple each of the contacts of the second semiconductor die to a respective contact of another one of the plurality of semiconductor dies.

10. The IC package of claim 9 , further comprising one or more wiring layers on the substrate and configured to couple each of the contacts of the second semiconductor die to a respective contact of another one of the plurality of semiconductor dies.

11. The IC package of claim 1 , wherein:
the first semiconductor die has an area equal to X units 2 ;
each contact is located in a respective contact area including Y units 2 of the X units 2 of the first semiconductor die; and
the number of N contacts is less than or equal to X/Y.

12. A method for inter-die communication in a multi-die IC package having data terminals for communication of data to and from the IC package comprising:
using a logic circuit on a first semiconductor die of the IC package, communicating M data signals in parallel with other dies of the IC package via M signal lines on the first semiconductor die; and
for each of a plurality of serializer circuits on the first semiconductor die:
serializing a respective first subset of the M data signals to produce a respective first serialized data signal; and
providing the respective first serialized data signal to a respective one of N contacts of the first semiconductor die, wherein N<M; and

for each of a plurality of deserializer circuits on the first semiconductor die:
deserializing a respective second serialized data signal on one of the N contacts to produce a respective second subset of the M data signals; and
providing each data signal of the respective second subset to a respective one of the M signal lines;

providing the first serialized data signal from the respective one of the N contacts to a second semiconductor die of the IC package;
using a deserializer circuit on the second semiconductor die, deserializing the first serialized data signal to produce a plurality of parallel data signals; and
using respective communication circuits

Assignees

• Xilinx Inc

Inventors

• Karp James
• Kireev Vassili

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title