Systems and methods for implementing error-shaping alias-free asynchronous flipping analog to digital conversion
US-2015365098-A1 · Dec 17, 2015 · US
US8994425B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994425-B2 |
| Application number | US-201213566882-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 3, 2012 |
| Priority date | Aug 3, 2012 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals.
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What is claimed is: 1. A circuit comprising: a first aligner circuit to align data indicated by a first input serial data signal with a phase of a first control signal to generate a first aligned serial data signal; a second aligner circuit to align data indicated by a second input serial data signal with the phase of the first control signal to generate a second aligned serial data signal; and a deskew circuit to remove skew between the first and the second aligned serial dat…
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