Method and system for providing tool induced shift using a sub-sampling scheme

Patent metadata

Field	Value
Publication number	US-9606453-B2
Application number	US-201113231333-A
Country	US
Kind code	B2
Filing date	Sep 13, 2011
Priority date	Sep 30, 2010
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

The present invention may include measuring tool induced shift (TIS) on at least one wafer of a lot of wafers via an omniscient sampling process, randomly generating a plurality of sub-sampling schemes, each of the set of randomly generated sub-sampling schemes having the same number of sampled fields, measuring TIS at each location of each of the randomly generated sub-sampling schemes, approximating a set of TIS values for each of the randomly generated sub-sampling schemes utilizing the TIS measurements from each of the randomly generated sub-sampling schemes, wherein each set of TIS values for each of the randomly generated sub-sampling schemes is calculated utilizing an interpolation process configured to approximate a TIS value for each location not included in a randomly generated sub-sampling scheme, and determining a selected sub-sampling scheme by comparing each of the calculated sets of TIS values to the measured TIS of the omniscient sampling process.

First claim

What is claimed:

1. A system for providing tool induced shift values across a semiconductor surface, comprising:
an overlay metrology tool configured to measure tool induced shift (TIS) on at least one wafer of a lot of wafers via a full sampling process, wherein the full sampling process includes measuring TIS at each measurement location of each field of the at least one wafer;
one or more processors communicatively coupled to the overlay metrology tool, wherein the one or more processors are configured to execute a set of program instructions configured to cause the one or more processors to execute the steps of:
randomly generating a plurality of sub-sampling schemes, wherein the number of fields to be sampled in each of the sub-sampling schemes is preselected, each of the set of randomly generated sub-sampling schemes having the same number of sampled fields, the number of sub-sampling schemes being preselected;
directing the overlay metrology tool to measure TIS at each location of each of the randomly generated sub-sampling schemes;
approximating a set of TIS values for each of the randomly generated sub-sampling schemes utilizing the TIS measurements from each of the randomly generated sub-sampling schemes, wherein each set of TIS values for each of the randomly generated sub-sampling schemes is calculated utilizing an interpolation process configured to approximate a TIS value for each location not included in a randomly generated sub-sampling scheme utilizing the TIS measured at each location of the randomly generated sub-sampling scheme;
identifying a preferred sub-sampling scheme, wherein the preferred sub-sampling scheme is the sub-sampling scheme of the plurality of randomly generated sub-sampling schemes that minimizes the difference between the calculated sets of TIS values and the measured TIS values of the full sampling process;
directing the overlay metrology tool to perform a TIS measurement according to the preferred sub-sampling scheme on at least one wafer of the lot of wafers via a full sampling process; and
providing a set of process tool correctables for use in a process tool, wherein the set of process tool correctables are calculated based on the TIS measurement performed according to the preferred sub-sampling scheme.

2. The system of claim 1 wherein the one or more processors are further configured to execute the steps of:
performing a subsequent TIS measurement with the overlay metrology tool on at least one wafer of a subsequent lot of wafers at each of the set of measurement locations of the generated selected sub-sampling scheme; and
approximating a TIS value for each of a set of measurement locations not included in the generated selected sub-sampling scheme of the at least one wafer of the subsequent lot of wafers utilizing one or more interpolation processes.

3. The system of claim 2 , wherein the approximating a TIS value for each of a set of measurement locations not included in the generated selected sub-sampling scheme of the at least one wafer of the subsequent lot of wafers utilizing one or more interpolation processes comprises:
approximating a TIS value for each of a set of measurement locations not included in the generated selected sub-sampling scheme of the at least one wafer of the subsequent lot of wafers utilizing one or more interpolation processes, wherein a portion of the one or more interpolation processes utilize a trainable history algorithm configured to incorporate information from previous interpolation processes.

4. The system of claim 1 , wherein the one or more processors are further configured to execute the steps of:
directing the overlay metrology tool to perform a subsequent TIS measurement on at least one wafer of a subsequent lot of wafers at one or more measurement locations of the set of measurement locations of the generated selected sub-sampling scheme;
calculating an average of two or more TIS values obtained from the one or more measurement locations of the set of measurement locations of the generated sub-sampling scheme; and
assigning the averaged two or more TIS values to all of the one or more measurement locations of the set of measurement locations of the generated selected sub-sampling scheme.

5. The system of claim 1 , wherein the generating a selected sub-sampling scheme by comparing each of the calculated sets of TIS values to the measured TIS of the full sampling process, wherein the sub-sampling scheme includes a set of measurement locations of the at least one wafer comprises:
generating a selected sub-sampling scheme by calculating a difference between each of the calculated sets of TIS values and the measured TIS of the full sampling process.

6. The system of claim 1 , wherein the generating a selected sub-sampling scheme by comparing each of the calculated sets of TIS values to the measured TIS of the full sampling process, wherein the sub-sampling scheme includes a set of field locations of the at least one wafer and a set of measurement locations within each field of the at least one wafer comprises:
generating a selected sub-sampling scheme by calculating a difference between each of the calculated sets of TIS values and the measured TIS of the full sampling process, wherein the preferred sub-sampling scheme is configured to provide a difference between the measured TIS of the sampling process and the approximated TIS below a preselected level.

7. The system of claim 1 , wherein the interpolation process includes at least one of Spline interpolation process, polynomial interpolation process, or neural network interpolation process.

8. The system of claim 1 , wherein the plurality of sub-sampling schemes are randomly generated with a Monte Carlo analysis process.

9. A system for providing tool induced shift values across a semiconductor surface, comprising:
an overlay metrology tool;
one or more processors communicatively coupled to the overlay metrology tool, wherein the one or more processors are configured to execute a set of program instructions configured to cause the one or more processors to execute the steps of:
generating a tool induced shift (TIS) sub-sampling scheme, wherein the TIS sub-sampling scheme is defined utilizing one or more statistical criterion, a selected number of sampling locations and a selected model type for TIS dependence across a semiconductor wafer surface, wherein the TIS subsampling scheme includes a set of measurement locations of the semiconductor wafer;
determining a first set of TIS values by directing the overlay metrology tool to acquire TIS values, at each of the measurement locations of the generated TIS subsampling scheme; and
determining a second set of TIS values by approximating TIS for each of a set of locations not included in the generated TIS sub-sampling scheme utilizing an interpolation process, wherein the interpolation process utilizes the first set of TIS values in order to calculate an approximated TIS value for each of the set of locations not included in the generated TIS sub-sampling scheme;
forming a full set of TIS values by combining the first set of TIS values and the second set of TIS values: and
providing a set of process tool correctables based on the full set of TIS values.

10. The system of claim 9 , wherein the generated TIS sub-sampling scheme includes a sub-set of available fields of a semiconductor wafer of a lot of wafers.

11. The system of claim 9 , wherein the generated TIS sub-sampling scheme includes a sub-set of measurement locations of available measurement locations in each field of a semiconductor wafer of a lot of wafers.

12. The system of claim 9 , wherein the number of sampling loca

Assignees

• Izikson Pavel
• Cohen Guy
• Kla Tencor Corp

Inventors

• Izikson Pavel
• Cohen Guy

Classifications

• H10P74/00 Primary

  Testing or measuring during manufacture or treatment of wafers, substrates or devices · CPC title

• G03F7/70616 Primary

  Monitoring the printed patterns · CPC title