SOI based FINFET with strained source-drain regions

Patent metadata

Field	Value
Publication number	US-9601624-B2
Application number	US-201414585742-A
Country	US
Kind code	B2
Filing date	Dec 30, 2014
Priority date	Dec 30, 2014
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A method of fabricating a semiconductor device where: (i) the fins are formed over a porous semiconductor material layer (for example, a silicon layer); and (ii) the porous semiconductor layer is then oxidized to form an insulator layer (for example, a SiO 2 buried oxide layer). The pores in the porous semiconductor layer facilitate reliable oxidation of the insulator layer by allowing penetration of gaseous oxygen (O 2 ) throughout the layer as it is oxidized to form the insulator layer. In some of these embodiments, a thin non-porous semiconductor layer is located over the porous semiconductor layer (prior to its oxidation) to allow strained epitaxial growth of material to be used in making source regions and drain regions of the finished semiconductor device (for example, a FINFET).

First claim

What is claimed:

1. A method of forming structures to be used in a semiconductor device, the method, comprising:
providing a pre-fin laminate structure including a set of base layer(s), a porous semiconductor layer and a fin-making layer, with the porous semiconductor layer being located on a top surface of the base layer(s), and with the fin-making layer being located on a top surface of the porous semiconductor layer;
refining the pre-fin laminate structure into a fin-bearing laminate structure by selectively removing material from the fin-making layer to form a set of fin structures, and a component-base layer over the porous semiconductor material layer in areas where fin structures are not present, from the material of the fin-making layer;
refining the fin-bearing laminate structure into a gate-bearing laminate structure by forming a set of gate structures with each gate structure of the set of gate structures extending over and across at least some of the fin structures;
refining the gate-bearing laminate structure into a component-bearing laminate structure by forming a component-making layer of semiconductor material in at least some areas bounded by a pair of fin structures and a pair of gate structures, wherein the component-making layer is composed of strained semiconductor material epitaxially grown on segmented top surfaces of the component-base layer in segments bounded by pairs of fin structures and pairs of gate structures;
selectively converting portions of the component-making layer into strained source regions and strained drain regions; and
refining the component-bearing laminate structure into a buried-insulator laminate structure by introducing reactive gas into pores of the porous semiconductor layer under conditions where the reactive gas reacts with the porous semiconductor layer to chemically change semiconductor material of the porous semiconductor layer into electrically insulative material.

2. The method of claim 1 wherein:
the fin-making layer is made of semiconductor material that contains silicon atoms.

3. The method of claim 1 wherein:
the fin-making layer of the pre-fin laminate structure, the fin structures of the fin-bearing laminate structure and the component-base layer of the fin-bearing laminate structure are made of silicon low doped with boron.

4. The method of claim 3 wherein:
the component-making layer is made of strained silicon germanium.

5. The method of claim 1 further comprising: selectively converting portions of the component-making layer into strained source regions and strained drain regions.

6. The method of claim 1 wherein:
the reactive gas includes oxygen (O 2 ); and
the refinement of the component-bearing laminate structure into the buried-insulator laminate structure oxidizes the porous semiconductor layer to chemically change the porous semiconductor into an electrically insulative oxide layer.

7. The method of claim 6 wherein:
the porous semiconductor layer of the pre-fin, fin-bearing, gate-bearing and component-bearing laminate structures is made of porous silicon; and
the refinement of the component-bearing laminate structure into the buried-insulator laminate structure oxidizes the porous silicon of the porous silicon layer to chemically change the porous silicon into electrically insulative silicon dioxide (SiO 2 ).

8. The method of claim 7 wherein:
in the refinement of the pre-fin structure into the fin-bearing laminate structure, the selective removal of material from the fin-making layer leaves a component-base layer over the porous semiconductor material layer in areas where fin structures are not present;
the component-base layer is made of silicon; and
the component-base layer is sufficiently thin so that the refinement of the component-bearing laminate structure into the buried-insulator laminate structure further oxidizes the component-base layer to chemically change the component-base layer into electrically insulative silicon dioxide (SiO 2 ).

9. The method of claim 1 wherein:
the refinement of the component-bearing laminate structure into the buried-insulator laminate structure is performed in a furnace at a high temperature.

10. The method of claim 1 wherein:
the chemical change of the refinement of the component-bearing laminate structure into the buried-insulator laminate structure at least substantially closes the pores of the porous semiconductor layer so that the buried insulator layer is at least substantially non-porous.

11. The method of claim 1 further comprising:
refining the buried-insulator laminate structure into an operational FINFET (fin-including field-effect transistor) device.

12. A method of forming structures to be used in a semiconductor device, the method, comprising:
providing a first laminate structure including a set of base layer(s) including at least a top base layer, where the top base layer is made of silicon;
refining the first laminate structure into a second laminate structure by epitaxially growing a highly-doped silicon layer on a top surface of the top base layer;
refining the second laminate structure into a third laminate structure by epitaxially growing a fin-making layer on a top surface of the highly-doped silicon layer, with the fin-making layer being made of semiconductor material;
refining the third laminate structure into a fourth laminate structure by performing a porousification process to form pores in the highly-doped silicon layer in order to change the highly-doped silicon layer into a porous silicon layer;
refining the fourth laminate structure into a fifth laminate structure by selectively removing material from the fin-making layer to form a set of fin structures from the material of the fin-making layer;
refining the fifth laminate structure into a sixth laminate structure by forming a set of gate structures with each gate structure of the set of gate structures extending over and across at least some of the fin structures;
refining the sixth laminate structure into a seventh laminate structure by growing by strained epitaxy a component-making layer of semiconductor material in at least some areas bounded by a pair of fin structures and a pair of gate structures; and
refining the seventh laminate structure into an eighth laminate structure by introducing oxygen gas into pores of the porous silicon layer at an elevated temperature to oxidize the silicon of the porous silicon layer and thereby changing the porous silicon layer into a buried oxide layer.

13. The method of claim 12 wherein:
the porousification process includes bathing the third laminate structure in a hydrogen fluoride (HF) bath.

14. The method of claim 13 wherein:
the porousification process further includes a hydrogen (H2) anneal to substantially close pores created in the fin-making layer and/or the set of base layer(s) by the HF bath.

15. The method of claim 12 wherein:
the top base layer is lightly doped with boron;
the highly-doped silicon layer is highly doped with boron; and
the fin-making layer is made of silicon lightly doped with boron.

16. The method of claim 15 wherein:
the top base layer is doped with boron at a concentration on the order of E18atoms per centimeter squared;
the highly-doped silicon layer is doped with boron at a concentration on the order of E20 atoms per centimeter squared; and
the fin-making layer is doped with boron at a concentration on the order of E18atoms per centimeter squared.

17. The method of claim 12 wherein:
in the refinement of the fourth structure into the fifth laminate

Assignees

• Globalfoundries Inc
• Globalfoundries Inc

Inventors

• Bedell Stephen W
• De Souza Joel P
• Fogel Keith E
• Reznicek Alexander
• Sadana Devendra K
• Schepis Dominic J

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6508

  by exposure to a liquid · CPC title

• H10P14/6502

  of treatments performed before formation of the materials · CPC title