Method for aligning micro-electronic components

Patent metadata

Field	Value
Publication number	US-9601459-B2
Application number	US-201414576637-A
Country	US
Kind code	B2
Filing date	Dec 19, 2014
Priority date	Dec 19, 2013
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid.

First claim

The invention claimed is:

1. A method for aligning a first micro-electronic component to a second micro-electronic component, wherein each component includes a contact area covered by a wetting layer, wherein each component includes a means for containing an alignment liquid on the respective wetting layer, and wherein each component is further provided with one or more conductor lines running along a circumference of the respective contact area, the method comprising:
applying an amount of the alignment liquid to the contact area of the second component;
placing the first component with its contact area facing the contact area of the second component so that the alignment liquid contacts both wetting layers, thereby establishing self-alignment of the contact areas through capillary force;
applying an electric potential such as to charge the conductor lines of at least one of the components in a manner to realize an electrostatic alignment of the contact areas; and
maintaining the electrostatic alignment while the alignment liquid evaporates.

2. The method according to claim 1 , wherein on at least one of the components, the means for containing a liquid on the wetting layers comprise at least one strip of anti-wetting material running along the circumference of the contact area.

3. The method according to claim 2 , wherein the conductor lines are embedded in or located on top of the strip of anti-wetting material.

4. The method according to claim 1 , wherein on at least one of the components, the means for maintaining a liquid on the wetting layers comprise a vertical sidewall surrounding the contact areas.

5. The method according to claim 1 , wherein on at least one of the components, the means for maintaining a liquid on the wetting layers comprises the conductor lines themselves, and wherein the conductor lines have been provided with anti-wetting properties.

6. The method according to claim 1 , wherein one of the components comprises a pair of conductor lines while the other component comprises a single conductor line, and wherein opposite electric potentials are applied to charge the pair of conductor lines, while no potential is applied to the single conductor line.

7. The method according to claim 6 , wherein the pair of conductor lines comprises interdigitated lateral extensions.

8. The method according to claim 1 , wherein each of the first and second components comprises at least one conductor line, and wherein first and second potentials are applied to charge the conductor line(s) of the first and second components, the first and second potentials being mutually opposite.

9. The method according to claim 1 , wherein the conductor lines on at least one of the components are present on top of the component.

10. The method according to claim 1 , wherein the conductor lines on at least one of the components are incorporated in a passivation layer that is a part of the component.

11. The method according to claim 1 , wherein the conductor lines of one of the components are located in a recess running around the circumference of the contact area of the component, and wherein the conductor lines of the other component are extending outwardly from the surface of the component, so that the alignment is further enhanced through a conformal lock and key mechanism.

12. The method for bonding a first micro-electronic component to a second micro-electronic component, wherein the first and second components are aligned according to the method of claim 1 , followed by the step of establishing a permanent bond between the components.

13. The method of claim 1 , wherein the first micro-electronic component includes a first bonding structure in the respective contact area, and the second micro-electronic component includes a second bonding structure in the respective contact area, further comprising bonding the first and second bond structures together.

14. The method of claim 13 , wherein at least one of first bonding structure or the second bonding structure includes a solder ball or microbump.

15. The method of claim 6 , wherein the single conductor line runs in a closed loop along the circumference of the respective contact area.

Assignees

• Imec Vzw
• Univ Leuven Kath

Inventors

• Dubey Vikas
• De Wolf Ingrid
• Beyne Eric

Classifications

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title