Vector register file

Patent metadata

Field	Value
Publication number	US-9594724-B2
Application number	US-201213570372-A
Country	US
Kind code	B2
Filing date	Aug 9, 2012
Priority date	Aug 9, 2012
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

An aspect includes accessing a vector register in a vector register file. The vector register file includes a plurality of vector registers and each vector register includes a plurality of elements. A read command is received at a read port of the vector register file. The read command specifies a vector register address. The vector register address is decoded by an address decoder to determine a selected vector register of the vector register file. An element address is determined for one of the plurality of elements associated with the selected vector register based on a read element counter of the selected vector register. A word is selected in a memory array of the selected vector register as read data based on the element address. The read data is output from the selected vector register based on the decoding of the vector register address by the address decoder.

First claim

What is claimed is:

1. A method for accessing a vector register in a vector register file, the method comprising:
receiving a read command at a read port of the vector register file, the read command specifying a vector register address, wherein a second read port of the vector register file is addressable to read a same element of the vector register address in parallel with the read port and the second read port is addressable to read a different vector register address in parallel with the read port;
decoding the vector register address by an address decoder to determine a selected vector register of the vector register file absent an element address to perform serialized access of the vector register file, wherein the vector register file comprises a plurality of vector registers and each vector register comprises a plurality of elements;
determining the element address for one of the plurality of elements associated with the selected vector register based on a read element counter of the selected vector register, wherein each vector register comprises a separate instance of the read element counter to independently retain state between instructions at each vector register;
selecting a word in a memory array of the selected vector register as read data based on the element address;
outputting the read data from the selected vector register based on the decoding of the vector register address by the address decoder;
incrementing the read element counter of the selected vector register to select a next sequential element in the memory array as the read data for one of: the read command and a next read command targeting the selected vector register;
performing the incrementing based on receiving an increment control signal at the selected vector register and based on the decoding of the vector register address by the address decoder;
based on incrementing the read element counter to select the next sequential element, prefetching the read data from the selected vector register for the next read command targeting the selected vector register prior to receiving the next read command targeting the selected vector register; and
outputting the prefetched read data based on receiving the next read command targeting the selected vector register.

2. The method of claim 1 , wherein the incrementing is performed after each iteration of a vector instruction to sequentially access the plurality of elements of the selected vector register.

3. The method of claim 1 , further comprising:
resetting the read element counter to select a first element in the memory array as the read data for one of: the read command and a next read command targeting the selected vector register; and
performing the resetting based on receiving a reset control signal at the selected vector register and based on the decoding of the vector register address by the address decoder.

4. The method of claim 1 , wherein the read port of the vector register file is one of a plurality of read ports coupled to the selected vector register, and further comprising:
receiving valid signals associated with each of the read ports at the selected vector register; and
performing the decoding of the vector register address by the address decoder in combination with the valid signals associated with each of the read ports.

5. The method of claim 1 , further comprising:
receiving a write command at a write port of the vector register file, the write command specifying the vector register address and write data;
decoding the vector register address by the address decoder to determine the selected vector register of the vector register file;
determining the element address for one of the plurality of elements associated with the selected vector register based on a write element counter of the selected vector register, wherein each vector register comprises a separate instance of the write element counter to independently retain state between instructions;
selecting an element in the memory array of the selected vector register to write based on the element address; and
writing the write data to the element of the selected vector register based on the decoding of the vector register address by the address decoder and the element address.

6. The method of claim 5 , further comprising:
reading a value of one or more of the read element counter and the write element counter based on receiving an element counter read command; and
writing the value of one or more of the read element counter and the write element counter based on receiving an element counter write command.

7. The method of claim 5 , wherein a total number of read and write ports of the vector register file is greater than a total number of read and write ports of the memory array.

8. The method of claim 7 , wherein each of the read and write ports of the vector register file has an associated increment control signal and an associated reset control signal to control incrementing and resetting of the read element counter and the write element counter on a port basis.

9. A method for accessing a vector register in a vector register file of a processing element in an active memory device, the method comprising:
receiving, in the processing element, a command from a requestor;
fetching, in the processing element, an instruction based on the command, the instruction being fetched from an instruction buffer in the processing element;
decoding, in the processing element, the instruction comprising a plurality of sub-instructions to execute in parallel, wherein at least one of the sub-instructions includes a read command targeting a vector register address of the vector register file;
receiving the read command at a read port of the vector register file, the read command specifying the vector register address, wherein a second read port of the vector register file is addressable to read a same element of the vector register address in parallel with the read port and the second read port is addressable to read a different vector register address in parallel with the read port;
decoding the vector register address by an address decoder to determine a selected vector register of the vector register file absent an element address to perform serialized access of the vector register file, wherein the vector register file comprises a plurality of vector registers and each vector register comprises a plurality of elements;
determining the element address for one of the plurality of elements associated with the selected vector register based on a read element counter of the selected vector register, wherein each vector register comprises a separate instance of the read element counter to independently retain state between instructions at each vector register;
selecting a word in a memory array of the selected vector register as read data based on the element address;
outputting the read data from the selected vector register based on the decoding of the vector register address by the address decoder;
incrementing the read element counter of the selected vector register to select a next sequential element in the memory array as the read data for one of: the read command and a next read command targeting the selected vector register;
performing the incrementing based on receiving an increment control signal at the selected vector register and based on the decoding of the vector register address by the address decoder;
based on incrementing the read element counter to select the next sequential element, prefetching the read data from the selected vector register for the next read command targeting the selected vector register prior to receiving the next read command targeting the selected vector register; and
outputting th

Assignees

• Fleischer Bruce M
• Fox Thomas W
• Jacobson Hans M
• Nair Ravi
• IBM

Inventors

• Fleischer Bruce M
• Fox Thomas W
• Jacobson Hans M
• Nair Ravi

Classifications

• G06F9/30109

  having multiple operands in a single register · CPC title

• G06F15/8076 Primary

  Details on data register access · CPC title

• G06F9/30098

  Register arrangements · CPC title

• G06F9/34

  Addressing or accessing the instruction operand or the result {; Formation of operand address; Addressing modes (address translation G06F12/00)} · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title