Execution of multi-byte memory access instruction specifying endian mode that overrides current global endian mode

Patent metadata

Field	Value
Publication number	US-9507595-B2
Application number	US-201414193491-A
Country	US
Kind code	B2
Filing date	Feb 28, 2014
Priority date	Feb 28, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

An aspect includes implementing endian-mode-sensitive memory instructions for a vector processor. One such system includes a byte addressable memory and a processor. The processor includes a register that includes a plurality of byte elements 0 to S. The system is configured to perform a method that includes obtaining an instruction by the processor and determining that the instruction is a memory access instruction specifying the register and a memory address. In response to the determination that the instruction is a memory access instruction and independent of a current global endian mode setting that is selectable in the processor, the memory access instruction is executed by copying the byte data between the memory and the register so that the byte element n of the register corresponds to the memory address+n for n=0 to S.

First claim

What is claimed is:

1. A computer system for copying data, the system comprising:
a memory that is byte addressable;
a processor including a first register that includes a plurality of byte elements 0 to S, the processor a bi-endian processor configurable to operate in a global endian mode when transferring data between the memory and the first register, the global endian mode setting selectable by the processor from the group consisting of a big-endian mode and a little-endian mode; and
a machine state register for specifying a current global endian mode setting of the processor;
wherein the system is configured to perform a method comprising:
obtaining, by the processor operating in the current global endian mode, an instruction;
determining that the instruction is a memory access instruction specifying the first register an endian mode, and further specifying a memory address; and
in response to the determination that the instruction is a memory access instruction overriding the current global endian mode and executing the memory access instruction by copying byte data between the memory and the first register so that the byte element n of the first register corresponds to the memory address+n for n=0 to S.

2. The computer system of claim 1 , where the first register corresponds to a vector register.

3. The computer system of claim 1 , wherein an element ordering used by the instruction is independent of the endian mode.

4. The computer system of claim 1 , wherein the current global endian mode of the processor is directly specified by a field in the memory access instruction.

5. The computer system of claim 1 , the method further comprising:
obtaining, by the processor, another instruction;
determining that the another instruction is a second memory access instruction specifying a second register having T byte elements and a second memory address; and
in response to the determination that the another instruction is a second memory access instruction and responsive to the current global endian mode setting, executing the second memory access instruction by copying byte data between the memory and the second register so that
responsive to a first endian mode being selected in the current global endian mode setting, a byte element n of the second register corresponds to memory address+n for n=0 to T, and
responsive to a second endian mode being selected in the current global endian mode setting a byte element T-n of the second register corresponds to memory address+n for n=0 to T.

6. The computer system of claim 1 , wherein the instruction corresponds to an endian-mode-independent load instruction and the another instruction corresponds to an endian-mode-sensitive load instruction.

7. The computer system of claim 1 , further including processing a data item with a computational instruction in an order dependent manner regardless of the current global endian mode setting.

8. The computer system of claim 1 , wherein the copying further comprises copying the byte data from the memory to the first register so that the byte data at memory address+n is copied to the byte element n of the first register for n=0 to S.

9. The computer system of claim 1 , wherein the copying further comprises copying the byte data from the first register to the memory so that the byte element n of the first register is copied to the memory address+n for n=0 to S.

10. A computer program product for copying data between a memory that is byte addressable and a vector register that includes a plurality of byte elements 0 to S, the computer program product comprising:
a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
obtaining, by a processor in a computer, a vector instruction, the processor operating in a current global endian mode and including a machine state register for specifying the current global endian mode setting of the processor, the processor a bi-endian processor configurable to operate in a global endian mode when transferring data between the memory and the vector register, the global endian mode setting selectable by the processor from the group consisting of a big-endian mode and a little-endian mode;
determining that the vector instruction is a memory access instruction specifying the vector register an endian mode and a memory address; and
in response to the determination that the instruction is a memory access instruction, overriding the current global endian mode and executing the memory access instruction by copying byte data between the memory and the vector register so that the byte element n of the vector register corresponds to the memory address+n for n=0 to S.

11. The computer program product of claim 10 , wherein the current global endian mode setting of the processor is overridden as specified in the memory access instruction.

Assignees

• IBM

Inventors

• Gschwind Michael K
• Olsson Brett

Classifications

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F15/8076

  Details on data register access · CPC title

• G06F9/30007

  to perform operations on data operands · CPC title

• G06F9/30098

  Register arrangements · CPC title

• G06F15/8061

  Details on data memory access · CPC title