Apparatus and method of vector unit sharing

Patent metadata

Field	Value
Publication number	US-9727526-B2
Application number	US-201113981851-A
Country	US
Kind code	B2
Filing date	Jan 25, 2011
Priority date	Jan 25, 2011
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A reconfigurable vector processor is described that allows the size of its vector units to be changed in order to process vectors of different sizes. The reconfigurable vector processor comprises a plurality of processor units. Each of the processor units comprises a control unit for decoding instructions and generating control signals, a scalar unit for processing instructions on scalar data, and a vector unit for processing instructions on vector data under control of control signals. The reconfigurable vector processor architecture also comprises a vector control selector for selectively providing control signals generated by one processor unit of the plurality of processor units to the vector unit of a different processor unit of the plurality of processor units.

First claim

What is claimed is:

1. A reconfigurable vector processor comprising:
a plurality of processor units, each comprising:
a scalar unit for processing instructions on scalar data;
a vector unit for processing instructions on vector data: and
a control unit for decoding instructions and generating control signals to control the scalar unit and the vector unit;

a vector control selector for selectively providing control signals generated by one of the control units of one of the plurality of processing units to a vector unit associated with a different processor unit of another one of the plurality of processor units to enable the vector unit associated with the different processor unit to be re-associated to and controlled by the one of the control units,
wherein the vector control selector comprises a vector control multiplexer associated with a first processor unit of the plurality of processor units for selectively coupling the vector unit of the first processor unit to the control unit of the first processor unit or to a control unit of a second processor unit of the plurality of processor units to selectively provide the one or more control signals generated by the first processor unit or the second processor unit to the vector unit of the first processor unit.

2. The reconfigurable vector processor of claim 1 , wherein the vector control selector comprises a crossbar switch for receiving a plurality of respective control signals from one or more of the plurality of processor units and selectively providing one or more of the received plurality of respective control signals to the respective vector units of one or more processor units of the plurality of processor units.

3. The reconfigurable vector processor architecture of claim 1 , further comprising a vector data connector for selectively coupling a data path of the vector unit of one of the plurality of processing units to a data path of the vector unit of the different processing unit of the plurality of processing units providing the control signals by the vector control selector.

4. The reconfigurable vector processor of claim 1 , further comprising a plurality of vector control selectors, each vector control selector comprising a vector control multiplexer associated with a respective vector unit of each of the plurality of processor units.

5. The reconfigurable vector processor of claim 4 , wherein the respective control units of one or more processor units are coupled to the vector control multiplexer associated with a different processor unit.

6. The reconfigurable vector processor of claim 5 , wherein the one or more of the processor units comprise a vector control multiplexer for selectively coupling the vector unit to the control unit of another processor unit.

7. The reconfigurable vector processor of claim 1 , wherein the scalar unit of each of the plurality of processor units can perform arithmetic, logical and shift operations.

8. The reconfigurable vector processor of claim 1 wherein each of the plurality of processor units further comprises an address generation unit component for generating the address of a next instruction to be executed by the processor unit.

9. The reconfigurable vector processor of claim 1 , wherein the scalar processor unit of each of the plurality of the processor units can operate concurrently with their respective vector units.

10. The reconfigurable vector processor of claim 1 , wherein the scalar unit of each of the processor units can operate autonomously from their respective vector units.

11. The reconfigurable vector processor of claim 1 , wherein one or more of the plurality of processor units each further comprise one or more data multiplexers for selectively coupling the vector units of the one or more processor units together.

12. The reconfigurable vector processor of claim 1 , wherein each vector unit comprises a plurality of computational units (CUs) each for processing data of a defined bit length.

13. The reconfigurable vector processor of claim 12 , wherein each CU is configured to perform add and shift operations on received data.

14. The reconfigurable vector processor of claim 12 , wherein each CU comprises:
a data register;
a plurality of bypass multiplexers coupled to the data register;
an arithmetic logic unit coupled to outputs of the plurality of bypass multiplexers;
a multiplication unit coupled to the outputs of the plurality of bypass multiplexers;
a load/store unit coupled to the outputs of the plurality of bypass multiplexers and a memory; and
a move/shift unit coupled to the outputs of the plurality of bypass multiplexers and one or more other computation units.

15. A method of processing data using a reconfigurable vector processor, the method comprising:
configuring one of a plurality of processing units of the processor to provide a vector array of a first size for processing data of the first size, the vector array provided by selectively associating vector units associated with different processing units of the plurality of processing units with the one of the plurality of processing units;
executing one or more instructions using the vector array of the first size to process data of the first size;
reconfiguring one of the plurality of processing units of the processor to change the vector array to a second size to process data of the second size by selectively re-associating vector units associated with different processing units of the plurality of processing units to the one or the plurality of processing units;
executing one or more instructions using the vector unit of the second size to process vector data of the second size;
selectively providing control signals generated by a control unit of one of the plurality of processing units to a vector unit associated with a different processor unit of another one of the plurality of processor units to enable the vector unit associated with the different processor unit to be re-associated to and controlled by the one of the control units.

16. The method of claim 15 , wherein configuring and reconfiguring the size of the vector processing unit comprises:
generating control signals for controlling a vector unit of a first processing unit of the plurality of processing units; and
providing the generated control signals to the vector unit of the first processing unit and a vector unit of a second processing unit to provide a vector array with a total size of a sum of individual vector units of the first and second processing units.

17. The method of claim 15 , wherein configuring one of a plurality of processing units of the processor comprises:
providing appropriate control signals to one or more components of the reconfigurable vector processor comprising a vector control multiplexer, or data multiplexers.

18. The method of claim 15 , further comprising:
executing instructions using one or more scalar processors of the reconfigurable vector processor when executing instructions using the vector unit associated with the different processor unit.

19. The method of claim 15 , further comprising:
configuring the reconfigurable vector processor to provide one or more additional vector units for processing vector data.

Assignees

• Stewart Malcolm
• Ors Ali Osman
• Laroche Daniel
• Nxp Usa Inc

Inventors

• Stewart Malcolm
• Ors Ali Osman
• Laroche Daniel

Classifications

• G06F15/7867 Primary

  with reconfigurable architecture · CPC title

• G06F15/8053

  Vector processors · CPC title

• G06F15/76 Primary

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title

• G06F9/30112

  comprising data of variable length · CPC title

• G06F15/8076

  Details on data register access · CPC title