Controlling non-redundant execution in a redundant multithreading (RMT) processor

Patent metadata

Field	Value
Publication number	US-9594648-B2
Application number	US-31780208-A
Country	US
Kind code	B2
Filing date	Dec 30, 2008
Priority date	Dec 30, 2008
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

In one embodiment, the present invention includes a method for controlling redundant execution such that if an exceptional event occurs, the redundant execution is stopped, non-redundant execution is performed in one of the threads until the exceptional event has been-resolved, after which a state of the threads is synchronized, and redundant execution is continued. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
an execution unit to execute instructions;
an order buffer having a plurality of entries each including an address field to store an address associated with an operation, a redundant mode field to store a redundant mode indicator to indicate whether the operation is to be executed during a redundant execution mode, the redundant mode indicator a single bit which, when a first value to indicate the redundant execution mode and when a second value to indicate a non-redundant execution mode, and a status field to store status information associated with the operation; and
a retirement unit to retire the executed instructions, the retirement unit comprising logic to control entry into and exit from the redundant execution mode, wherein the processor is to redundantly execute first instructions of a program in a first thread and a second thread in the redundant execution mode under control of the logic, wherein the logic is to terminate the redundant execution mode when the retirement unit detects an exceptional event, generate a trigger event for the non-redundant execution mode to control switching from the redundant execution mode to the non-redundant execution mode, cause only the first thread to execute second instructions of the program to resolve an exceptional condition associated with the exceptional event and to continue execution of the second instructions past resolution of the exception condition until a specific condition is met, synchronize a state of the first thread and a state of the second thread after the second instructions, and redundantly execute third instructions of the program in the first and second threads in the redundant execution mode, the third instructions different than the first and second instructions.

2. The processor of claim 1 , wherein the logic is to cause the first thread to execute the second instructions, wherein the first thread is a primary thread.

3. The processor of claim 2 , wherein the logic is to trigger the non-redundant execution mode upon detection of the exceptional condition.

4. The processor of claim 3 , wherein the logic is to determine that the exceptional condition is resolved.

5. The processor of claim 1 , wherein the logic is to set the redundant mode if the operation was executed in the redundant execution mode.

6. The processor of claim 1 , wherein the processor is to mark instructions executed in the non-redundant execution mode with a non-redundant indicator to prevent cross-thread checking of results of the non-redundantly executed instructions.

7. The processor of claim 1 , wherein the processor is a multithreaded processor and the first thread and the second thread are to execute on a core of the multithreaded processor.

8. The processor of claim 7 , wherein the processor is to copy a register file of the first thread to a register file of the second thread to synchronize the thread states, and if a portion of non-register architectural state of the first thread is modified in the non-redundant execution mode, copy the portion of the non-register architectural state of the first thread to the second thread.

9. The processor of claim 1 , wherein the redundant execution mode termination is to occur responsive to a user-level instruction of an instruction set architecture (ISA) that enables the redundant execution mode termination.

10. The processor of claim 1 , wherein the redundant execution mode termination is to occur responsive to a privileged instruction of an instruction set architecture (ISA) that enables the redundant execution mode termination.

11. A system comprising:
a multi-core processor including at least a first core and a second core, wherein the first core includes at least one execution unit and retirement logic to retire a first set of instructions of a program executed in a first thread and a second redundant thread in a redundant execution mode in the first core, the first core to, responsive to a first user-level redundant mode exit instruction of an instruction set architecture (ISA), exit from the redundant execution mode, perform non-redundant execution in a non-redundant execution mode of a second set of instructions of the program in only the first thread until receipt of a second user-level redundant mode entry instruction of the ISA to enter into the redundant execution mode, synchronize a state of the first thread and the second redundant thread, and perform continued redundant execution of a third set of instructions of the program in the first thread and the second redundant thread in the redundant execution mode, wherein the first core includes an order buffer to store information associated with an operation, the information including a redundant indicator comprising a single bit having a given one of a first value to indicate that the operation was executed in the redundant execution mode and a second value to indicate that the operation was executed in the non-redundant execution mode; and
a dynamic random access memory (DRAM) coupled to the multi-core processor.

12. The system of claim 11 , wherein the first core is to set the redundant indicator if the operation was executed in the redundant execution mode.

Assignees

• Hinton Glenn J
• Raasch Steven E
• Hily Sebastien
• Holm John G
• Singhal Ronak
• Sodani Avinash
• Marr Deborah T
• Intel Corp

Inventors

• Hinton Glenn J
• Raasch Steven E
• Hily Sebastien
• Holm John G
• Singhal Ronak
• Sodani Avinash
• Marr Deborah T

Classifications

• G06F11/1683 Primary

  at instruction level · CPC title

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F11/1658

  Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit · CPC title

• G06F11/1641

  where the comparison is not performed by the redundant processing components · CPC title

• G06F9/30189

  according to execution mode, e.g. mode flag · CPC title