Method for manufacturing a FinFET device

Patent metadata

Field	Value
Publication number	US-9590076-B1
Application number	US-201414402303-A
Country	US
Kind code	B1
Filing date	Aug 1, 2014
Priority date	May 12, 2014
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

A method for manufacturing a FinFET device, including providing a substrate; implementing a source/drain doping on the substrate; etching the doped substrate to form a source region and a drain region; forming a fin channel between the source region and the drain region; and forming a gate on the Fin channel. The fin and the gate are formed after the source/drain doping is implemented on the substrate, so that the source/drain doping is done as a doping for a planar device, which ensures the quality of the source/drain coping and improves the property of the FinFET device.

First claim

We claim:

1. A method for manufacturing a FinFET device, comprising:
providing a substrate;
implementing a source/drain doping on the substrate;
etching the doped substrate to form a source region and a drain region;
forming a fin channel between the source region and the drain region; and forming a gate on the Fin channel;
wherein the step of forming a fin channel between the source region and the drain region comprises:
forming a dielectric layer on the substrate except for the source region and the drain region;
planarizing until exposing the source region and the drain region;
etching the dielectric layer between the source region and the drain region to form a fin channel region in the dielectric layer;
forming a fin channel within the fin channel region; and
removing the dielectric layer with some certain thickness and the remaining dielectric layer functions as an isolation structure.

2. The method according to claim 1 , wherein the fin channel is formed in the fin channel region by a selectively epitaxial growth.

3. The method according to claim 1 , wherein the source/drain doping on the substrate is implemented by an ion implantation or an epitaxial doping.

4. The method according to claim 1 , wherein the doping concentration for the source and drain regions is larger than 1e20 cm−3.

Assignees

• Inst Of Microelectronics Cas

Inventors

• Liu Jinbiao
• Wang Yao
• Wang Guilei
• Yang Tao
• Liu Qing
• Li Junfeng

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title