Fin field effect transistor including a strained epitaxial semiconductor shell

Patent metadata

Field	Value
Publication number	US-9391171-B2
Application number	US-201414162933-A
Country	US
Kind code	B2
Filing date	Jan 24, 2014
Priority date	Jan 24, 2014
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

A semiconductor fin including a single crystalline semiconductor material is formed on a dielectric layer. A semiconductor shell including an epitaxial semiconductor material is formed on all physically exposed surfaces of the semiconductor fin by selective epitaxy, which deposits the semiconductor material only on semiconductor surfaces and not on dielectric surfaces. The epitaxial semiconductor material can be different from the single crystalline semiconductor material, and the semiconductor shell can be bilaterally strained due to lattice mismatch. A fin field effect transistor including a strained channel can be formed. Further, the semiconductor shell can advantageously alter properties of the source and drain regions, for example, by allowing incorporation of more dopants or by facilitating a metallization process.

First claim

What is claimed is:

1. A method of forming a semiconductor structure comprising:
forming a semiconductor fin including a first semiconductor material on an insulator layer, said semiconductor fin laterally bounded by a pair of parallel lengthwise sidewalls and a pair of parallel widthwise sidewalls; and
forming an epitaxial semiconductor shell comprising a second semiconductor material with epitaxially alignment with said first semiconductor material on all surfaces of said pair of parallel lengthwise sidewalls and said pair of parallel widthwise sidewalls, wherein said semiconductor fin further comprises a planar top surface having a periphery that coincides with top edges of said pair of parallel lengthwise sidewalls and said pair of parallel widthwise sidewalls, and said epitaxial semiconductor shell is formed directly on said planar top surface.

2. The method of claim 1 , wherein said epitaxial semiconductor shell is formed by selective epitaxy of said second semiconductor material.

3. The method of claim 1 , further comprising forming a stack of a gate dielectric and a gate electrode over a combination of said semiconductor fin and said epitaxial semiconductor shell.

4. The method of claim 3 , further comprising implanting electrical dopants into portions of said semiconductor fin and said epitaxial semiconductor shell employing at least said stack as an implantation mask, wherein implanted portions of said semiconductor fin and said epitaxial semiconductor shell include a source region and a drain region.

5. The method of claim 1 , wherein said second semiconductor material is lattice mismatched with respect to said first semiconductor material, and said epitaxial semiconductor shell is biaxially strained in directions parallel to a proximal interface with said semiconductor fin.

6. The method of claim 1 , wherein said first and second semiconductor materials are selected from single crystalline silicon, a single crystalline silicon-germanium alloy, a single crystalline silicon-carbon alloy, and a single crystalline silicon-germanium-carbon alloy.

7. The method of claim 1 , further comprising:
forming another semiconductor fin including a third semiconductor material on said insulator layer, said another semiconductor fin laterally bounded by another pair of parallel lengthwise sidewalls and another pair of parallel widthwise sidewalls; and
forming another epitaxial semiconductor shell comprising a fourth semiconductor material with epitaxial alignment with said third semiconductor material on all surfaces of said another pair of parallel lengthwise sidewalls and said another pair of parallel widthwise sidewalls.

8. The method of claim 7 , wherein one of said epitaxial semiconductor shell and said another epitaxial semiconductor shell has a biaxial compressive strain within a plane that is parallel to a proximal interface with said semiconductor fin, and another of said epitaxial semiconductor shell and said another epitaxial semiconductor shell has a biaxial tensile strain within a plane that is parallel to a proximal interface with said another semiconductor fm.

9. The method of claim 7 , wherein said first semiconductor material is single crystalline silicon, said second semiconductor material is a single crystalline silicon-germanium alloy, said third semiconductor material is another single crystalline silicon-germanium alloy, and said fourth semiconductor material is single crystalline silicon.

10. A method of forming a semiconductor structure comprising:
forming a semiconductor fin including a first semiconductor material on an insulator layer, said semiconductor fin laterally bounded by a pair of parallel lengthwise sidewalls and a pair of parallel widthwise sidewalls;
forming an epitaxial semiconductor shell comprising a second semiconductor material with epitaxially alignment with said first semiconductor material on all surfaces of said pair of parallel lengthwise sidewalls and said pair of parallel widthwise sidewalls;
forming another semiconductor fin including a third semiconductor material on said insulator layer, said another semiconductor fin laterally bounded by another pair of parallel lengthwise sidewalls and another pair of parallel widthwise sidewalls; and
forming another epitaxial semiconductor shell comprising a fourth semiconductor material with epitaxial alignment with said third semiconductor material on all surfaces of said another pair of parallel lengthwise sidewalls and said another pair of parallel widthwise sidewalls.

Assignees

• IBM

Inventors

• Chan Kevin K
• Kim Young-Hee
• Kobayashi Masaharu
• Li Jinghong
• Park Dae-Gyu

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/3458

  Monocrystalline · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3408

  Silicon carbide · CPC title