Implementing resistance defect performance mitigation using test signature directed self heating and increased voltage

Patent metadata

Field	Value
Publication number	US-9583403-B2
Application number	US-201514840163-A
Country	US
Kind code	B2
Filing date	Aug 31, 2015
Priority date	Jun 25, 2015
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

A method and system are provided for implementing resistive defect performance mitigation for integrated circuits. A test is generated for identifying resistive defects. A first self heating repair process is performed for repairing resistive defects. Testing is performed to identify a mitigated resistive defect and a functional integrated circuit. Responsive to identifying a resistive defect not being mitigated and a functional integrated circuit, a second repair process is performed, then testing is performed again.

First claim

What is claimed is:

1. A method for implementing resistive defect performance mitigation for integrated circuits in a computer system comprising:
providing a test generator for identifying resistive defects;
performing a first self heating repair process for repairing resistive defects;
performing testing to identify a mitigated resistive defect and a functional integrated circuit; and
responsive to identifying a resistive defect not being mitigated and a functional integrated circuit, performing a second repair process, and repeating testing to identify a mitigated resistive defect and a functional integrated circuit.

2. The method as recited in claim 1 wherein the first self heating repair process includes repeatedly switching a signal to a circuit path containing the resistive defect at a selected frequency and a selected voltage for a set duration.

3. The method as recited in claim 2 wherein said selected frequency is approximately equal or slightly above a maximum frequency at which the integrated circuit functions, and said set duration equals a set number of microseconds allowing millions of switches.

4. The method as recited in claim 2 wherein the repeated switching is provided at a set elevated voltage to enhance localized heating and stressing of any residual dielectric films in the connecting area.

5. The method as recited in claim 1 wherein repairing resistive defects includes one or more of repairing resistive connections in a contact, a via, and a high resistance defect present in an internally embedded interconnect.

6. The method as recited in claim 1 wherein performing testing to identify a mitigated resistive defect and a functional integrated circuit includes applying an appropriate voltage for use of the integrated circuit to a defect node, and testing to identify a mitigated resistive defect and a functional integrated circuit.

7. The method as recited in claim 1 wherein said second repair process includes at least one of using a laser to enhance the local heating, and providing incremental voltage steps to a defect node and repeating until a maximum voltage is reached.

8. The method as recited in claim 1 includes identifying a successful repair, responsive to identifying a resistive defect being mitigated and a functional integrated circuit being identified.

9. The method as recited in claim 8 includes discarding the integrated circuit, responsive to a functional integrated circuit not being identified.

Assignees

• IBM

Inventors

• Erickson Karl R
• Paone Phil C
• Paulsen David P
• Sheets Ii John E
• Uhlmann Gregory J

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P74/232 Primary

  comprising connection or disconnection of parts of a device in response to a measurement · CPC title

• G01R31/2868

  Complete testing stations; systems; procedures; software aspects · CPC title

• G01R31/2894 Primary

  Aspects of quality control [QC] (G01R31/31718 takes precedence; program control for QC G05B19/41875) · CPC title