Element embedded printed circuit board and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9578749-B2
Application number	US-201514943866-A
Country	US
Kind code	B2
Filing date	Nov 17, 2015
Priority date	Nov 18, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

An element embedded printed circuit board includes: a substrate including an insulation layer, a first circuit layer formed on a first surface of the insulation layer, and a second circuit layer formed on a second surface of the insulation layer; and an element including an electrode part and embedded in the insulation layer, wherein the electrode part is in contact with the first circuit layer.

First claim

What is claimed is:

1. An element embedded printed circuit board comprising: a substrate comprising an insulation layer, a first circuit layer formed on a first surface of the insulation layer, and comprising an embedded pattern formed inside the insulation layer and a protruding pattern formed outside the insulation layer, and a second circuit layer formed on a second surface of the insulation layer; an element embedded in the insulation layer and comprising an electrode part in contact with the first circuit layer; and a conductive adhesive layer disposed between the electrode part and the protruding pattern.

2. The element embedded printed circuit board of claim 1 , further comprising a non-conductive adhesive layer formed on an outside surface of the element, wherein the first circuit layer is formed on the outside surface of the element.

3. The element embedded printed circuit board of claim 1 , wherein the embedded circuit pattern comprises a circuit pattern formed on an outside of the element.

4. The element embedded printed circuit board of claim 1 , further comprising a micro via providing electrical connection between the electrode part and the second circuit layer.

5. The element embedded printed circuit board of claim 1 , further comprising a penetration via providing electrical connection between the first circuit layer and the second circuit layer.

6. The element embedded printed circuit board of claim 1 , wherein the element is a passive element.

7. A method of manufacturing an element embedded printed circuit board, comprising: preparing a carrier member comprising an element mounting portion and a circuit portion formed on at least one of a first surface thereof or a second surface thereof; forming a first circuit pattern on the circuit portion; mounting an element on the element mounting portion, the element comprising an electrode part; forming a laminated body by laminating an insulation layer on the carrier member; separating the laminated body from at least a portion of the carrier member; and forming a first circuit layer on a first surface of the laminated body and forming a second circuit layer on a second surface of the laminated body, the first circuit layer comprising a second circuit pattern in contact with the electrode part, wherein the first circuit pattern comprises an embedded pattern formed inside the insulation layer, the second circuit pattern comprises a protruding pattern formed outside the insulation layer, wherein the mounting of the element comprises, before the element is mounted, forming a conductive adhesive layer on the carrier member at areas where the electrode part is to be in contact with the carrier member, and wherein the conductive adhesive layer is disposed between the electrode part and the protruding pattern after the separation of the laminated body from at least a portion of the carrier member.

8. The method of claim 7 , wherein the mounting of the element comprises, before the element is mounted, forming a non-conductive adhesive layer on the carrier member at areas where the element is to be mounted in contact with the carrier member.

9. The method of claim 7 , wherein a cavity for accommodating the element is formed in the insulation layer.

10. The method of claim 7 , wherein the first circuit pattern comprises a circuit pattern formed on an outside surface of the element.

11. The method of claim 7 , further comprising: forming micro vias providing electrical connection between the electrode part and the second circuit layer; and forming penetration vias providing electrical connection between the first circuit layer and the second circuit layer.

12. The method of claim 7 , wherein the element is a passive element.

13. The method of claim 7 , further comprising forming a solder resist layer on the first surface of the laminated body and the second surface of the laminated body.

14. The method of claim 7 , further comprising: coating a metal material on an outside surface of the electrode part before the element is mounted; and melting the metal material, after the element is mounted, to couple the electrode part to the first circuit layer.

Assignees

• Samsung Electro Mech

Inventors

• Cho Jung-Hyun
• Baek Yong-Ho
• Ko Young-Gwan
• Choi Jae-Hoon
• Park Jung-Hyun

Classifications

• H10W72/9413

  on encapsulations · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H05K3/007 Primary

  Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier (H05K1/187, H05K3/20 and H05K3/4682 take precedence) · CPC title