Silver alloying post-chip join

Patent metadata

Field	Value
Publication number	US-9576922-B2
Application number	US-201514702984-A
Country	US
Kind code	B2
Filing date	May 4, 2015
Priority date	May 4, 2015
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A method of forming a stacked surface arrangement for semiconductor devices includes joining a first surface to a second surface with a solder bump, the solder bump including a substantially pure first metal; depositing nanoparticles of a second metal onto a surface of the solder bump; performing an annealing operation to form a film of the second metal on the surface of the solder bump; and performing a reflow or a second annealing operation to transform the solder bump from the substantially pure first metal to an alloy of the first metal and the second metal.

First claim

What is claimed is:

1. A method of forming a stacked surface arrangement for semiconductor devices, the method comprising:
joining a first surface to a second surface with a solder bump, the solder bump comprising a substantially pure first metal;
after the joining, depositing a film of a second metal onto an exposed surface of the solder bump by injecting a nanosuspension comprising nanoparticles of the second metal between the first surface and the second surface around the exposed surface of the solder bump and performing an annealing operation; and
performing a reflow operation or a second annealing operation to transform the solder bump from the substantially pure first metal to an alloy of the first metal and the second metal.

2. The method of claim 1 , the first surface and the second surface comprising hydrophobic polymeric layers that cause the nanosuspension to retract during the anneal operation, ensuring that the film of the second metal only deposits onto the exposed surface of the solder bump and not the first surface and the second surface.

3. The method of claim 1 , the annealing operation causing a solvent from the nanosuspension to evaporate and the nanoparticles to deposit onto the exposed surface of the solder bump by capillary action.

4. The method of claim 1 , wherein the first metal is tin (Sn).

5. The method of claim 1 , wherein the second metal is silver (Ag).

6. The method of claim 1 , further comprising forming an underfill material around the solder bump after the performing of the annealing operation and before the performing of the reflow operation.

7. The method of claim 1 , wherein the alloy is an SnAg alloy and includes at least 2 wt. % silver.

8. A method of forming a stacked surface arrangement for semiconductor devices, the method comprising:
joining a first surface to a second surface with solder bumps comprising a substantially pure first metal;
after the joining, depositing a film of a second metal onto exposed surfaces of the solder bumps by injecting a nanosuspension comprising nanoparticles of the second metal between the first surface and the second surface around the exposed surfaces of the solder bumps and performing an annealing operation;
forming an underfill material around the solder bumps to fill gaps between the solder bumps; and
after the forming of the underfill material around the solder bumps, performing a reflow operation to transform the solder bumps from the substantially pure first metal to an alloy of the first metal and the second metal.

9. The method of claim 8 , the annealing operation causing a solvent from the nanosuspension to evaporate and the nanoparticles to deposit onto the exposed surfaces of the solder bump by capillary action.

10. The method of claim 8 , wherein the nanoparticles selectively assemble on the exposed surfaces of the solder bumps.

11. The method of claim 10 , wherein tin oxide is present on the exposed surfaces of the solder bumps and then the nanoparticles selectively assembly on the exposed surfaces.

12. The method of claim 8 , wherein the film has a thickness in a range from about 100 nm to about 1000 nanometers (nm).

13. The method of claim 8 , wherein the second metal is silver.

14. The method of claim 8 , wherein the substantially pure first metal is tin.

15. The method of claim 8 , wherein the annealing operation is performed at a temperature of at least 100° Celsius (° C.).

16. The method of claim 8 , further comprising wet etching to remove nanoparticles from gaps between the solder bumps.

17. The method of claim 8 , the first surface and the second surface comprising hydrophobic polymeric layers that cause the nanosuspension to retract during the anneal operation, ensuring that the film of the second metal only deposits onto the exposed surface of the solder bump and not the first surface and the second surface.

18. A method of forming a stacked surface arrangement for semiconductor devices, the method comprising:
joining a first surface to a second surface with a solder bump, the solder bump comprising a substantially pure first metal;
after the joining, selectively depositing a film of a second metal onto an exposed surface of the solder bump such that, following the depositing of the film, the first surface and the second surface remain free of the film, the selectively depositing comprising:
injecting a nanosuspension comprising nanoparticles of the second metal between the first surface and the second surface around the exposed surface of the solder bump; and
performing an annealing operation; and

performing a reflow operation to transform the solder bump from the substantially pure first metal to an alloy of the first metal and the second metal.

19. The method of claim 18 ,
the first metal comprising tin (Sn),
the second metal comprising silver (Ag), and
the first surface and the second surface comprising hydrophobic polymeric layers that cause the nanosuspension to retract during the anneal operation, ensuring that the film of the second metal only deposits onto the exposed surface of the solder bump and not the first surface and the second surface.

20. The method of claim 18 , the annealing operation causing a solvent from the nanosuspension to evaporate and the nanoparticles to deposit onto the exposed surface of the solder bump by capillary action.

Assignees

• Globalfoundries Inc

Inventors

• Brunschwiler Thomas J
• Perfecto Eric D
• Zuercher Jonas

Classifications

• H10W95/00

  Packaging processes not covered by the other groups of this subclass · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07255

  changes in materials · CPC title

• H10W72/07236

  Soldering or alloying · CPC title