Printed circuit board and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9572250-B2
Application number	US-201113997464-A
Country	US
Kind code	B2
Filing date	Dec 23, 2011
Priority date	Dec 24, 2010
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

Disclosed are a printed circuit board and a method for manufacturing the same. The printed circuit board includes a core insulating layer, at least one via formed through the core insulating layer, an inner circuit layer buried in the core insulating layer, and an outer circuit layer on a top surface or a bottom surface of the core insulating layer, wherein the via includes a first part, a second part below the first part, a third part between the first and second parts, and at least one barrier layer including a metal different from a metal of the first to third parts. The inner circuit layer and the via are simultaneously formed so that the process steps are reduced. Since odd circuit layers are provided, the printed circuit board has a light and slim structure.

First claim

The invention claimed is:

1. A printed circuit board comprising:
a first insulating layer;
a second insulating layer below the first insulating layer;
a via formed through the first insulating layer and the second insulating layer;
an inner circuit layer on the second insulating layer and buried in the first insulating layer; and
an outer circuit layer on a top surface of the first insulating layer or a bottom surface of the second insulating layer;
wherein the via includes:
a first part,
a second part below the first part,
a third part between the first and second parts,
a first barrier layer between the first part and the third part, and
a second barrier layer between the third part and the second part;
wherein a side surface of the third part of the via has a first predetermined inclination angle with respect to a top surface of the first insulating layer;
wherein the inner circuit layer includes:
a third barrier layer on the second insulating layer and horizontally spaced apart from the via, and
an inner circuit pattern on the third barrier layer and horizontally spaced apart from the via;
wherein a bottom surface of the third barrier layer is at a same level as a top surface of the second part;
wherein the via has a hexagon sectional shape;
wherein a shape of the third barrier layer is same as a shape of the second barrier layer, and a shape of the inner circuit pattern is same as a shape of the third part; and
wherein the inner circuit pattern and the third barrier layer each has a trapezoid sectional shape.

2. The printed circuit board of claim 1 , wherein the inner circuit pattern is formed with a material identical to a material of the third part of the via.

3. The printed circuit board of claim 1 , wherein the first part, the second part, and the third part of the via are formed with a same material.

4. The printed circuit board of claim 1 ,
wherein the first, second and third barrier layers are formed with a same material.

5. The printed circuit hoard of claim 1 , wherein the printed circuit board comprises a circuit layer including the inner circuit layer and the outer circuit layer and having a number of 2n+1 (n is a positive integer).

6. The printed circuit board of claim 1 , further comprising an adhesive layer formed on the top surface of the first insulating layer or the bottom surface of the second insulating layer with clearance to expose the via.

7. The printed circuit board of claim 6 , wherein the adhesive layer includes primer resin.

8. The printed circuit board of claim 1 , wherein a side surface of the first part of the via has a second predetermined inclination angle with respect to the top surface of the first insulating layer, and
wherein the first predetermined inclination angle is same as the second predetermined inclination angle.

9. The printed circuit board of claim 4 , wherein a width of a top surface of the third part is same as a width of the bottom surface of the first barrier layer.

10. The printed circuit board of claim 6 , wherein the outer circuit layer comprises a seed layer on the adhesive layer.

11. The printed circuit board of claim 10 , wherein the seed layer comprises a first bottom surface contacting with a top surface of the adhesive layer and a second bottom surface contacting with a top surface of the first part of the via.

12. The printed circuit board of claim 6 , wherein the adhesive layer is contacted with a side surface of the first part of the via.

13. The printed circuit board of claim 12 , wherein a top surface of the adhesive layer portions lies on a same plane as a top surface of the first part of the via.

Assignees

• Lee Sang Myung
• Yoon Sung Woon
• Lee Hyuk Soo
• Lee Sung Won
• Chun Ki Do
• Lg Innotek Co Ltd

Inventors

• Lee Sang Myung
• Yoon Sung Woon
• Lee Hyuk Soo
• Lee Sung Won
• Chun Ki Do

Classifications

• H05K3/388

  by the use of a metallic or inorganic thin film adhesion layer · CPC title

• H05K2201/0341

  Intermediate metal, e.g. before reinforcing of conductors by plating · CPC title

• H05K2203/0376

  Etching temporary metallic carrier substrate · CPC title

• H05K3/4647

  by applying an insulating layer around previously made via studs · CPC title

• H05K3/064

  Photoresists · CPC title