Power semiconductor package with integrated heat spreader and partially etched conductive carrier

US9570379B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9570379-B2
Application numberUS-201414546762-A
CountryUS
Kind codeB2
Filing dateNov 18, 2014
Priority dateDec 9, 2013
Publication dateFeb 14, 2017
Grant dateFeb 14, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In one implementation, a power semiconductor package includes a power transistor having a first power electrode and a gate electrode on its bottom surface, and a second power electrode on its top surface. The first power electrode is configured for attachment to a first partially etched conductive carrier segment and the gate electrode is configured for attachment to a second partially etched conductive carrier segment. The power semiconductor package also includes a power electrode heat spreader situated over the second power electrode and configured for attachment to a power electrode conductive carrier segment.

First claim

Opening claim text (preview).

The invention claimed is: 1. A power semiconductor package comprising: a power transistor that includes a first power electrode and a gate electrode on a bottom surface of said power transistor, and a second power electrode on a top surface of said power transistor; said first power electrode that is configured for attachment to a first partially etched conductive carrier segment; said gate electrode that is configured for attachment to a second partially etched conductive carrier segment; a power electrode heat spreader that is configured to electrically couple said second power electrode to a power electrode conductive carrier segment; and a gate electrode heat spreader that has a contact surface, wherein the gate electrode heat spreader is configured to contact said gate electrode and a gate electrode carrier segment along said contact surface to electrically couple said gate electrode to said gate electrode carrier segment. 2. The power semiconductor package of claim 1 , wherein said first partially etched conductive carrier segment, said second partially etched conductive carrier segment, and said power electrode conductive carrier segment are configured for attachment to a substrate. 3. The power semiconductor package of claim 2 , wherein said substrate is a circuit board. 4. The power semiconductor package of claim 1 , wherein said power transistor is selected from the group consisting of a FET, an IGBT, and a HEMT. 5. The power semiconductor package of claim 1 , wherein said power transistor is selected from the group consisting of a silicon FET and a GaN FET. 6. The power semiconductor package of claim 1 , wherein said first power electrode is a source electrode. 7. The power semiconductor package of claim 1 , wherein said second power electrode is a drain electrode. 8. The power semiconductor package of claim 1 , wherein said power transistor is part of a voltage converter. 9. The power semiconductor package of claim 1 , wherein said power semiconductor package is encapsulated in a molding compound. 10. The power semiconductor package of claim 1 , wherein said power electrode conductive carrier segment is thicker than said first and said second partially etched conductive carrier segments. 11. A power semiconductor package comprising: a power transistor that includes a first power electrode and a gate electrode on a top surface of said power transistor, and a second power electrode on a bottom surface of said power transistor; said second power electrode that is configured for attachment to a partially etched conductive carrier segment; a power electrode heat spreader that is configured to electrically couple said first power electrode to a power electrode conductive carrier segment; and a gate electrode heat spreader that has a contact surface, wherein the gate electrode heat spreader is configured to contact said gate electrode and a gate electrode carrier segment along said contact surface to electrically couple said gate electrode to said gate electrode carrier segment. 12. The power semiconductor package of claim 11 , wherein said partially etched conductive carrier segment, said power electrode conductive carrier segment, and said gate electrode conductive carrier segment are configured for attachment to a substrate. 13. The power semiconductor package of claim 12 , wherein said substrate is a circuit board. 14. The power semiconductor package of claim 11 , wherein said power transistor is selected from the group consisting of a FET, an IGBT, and a HEMT. 15. The power semiconductor package of claim 11 , wherein said power transistor is selected from the group consisting of a silicon FET and a GaN FET. 16. The power semiconductor package of claim 11 , wherein said first power electrode is a source electrode. 17. The power semiconductor package of claim 11 , wherein said second power electrode is a drain electrode. 18. The power semiconductor package of claim 11 , wherein said power transistor is part of a voltage converter. 19. The power semiconductor package of claim 11 , wherein said power semiconductor package is encapsulated in a molding compound. 20. The power semiconductor package of claim 11 , wherein said power electrode conductive carrier segment and said gate electrode conductive carrier segment are thicker than said first and said second partially etched conductive carrier segments. 21. The power semiconductor package of claim 1 , wherein said gate electrode heat spreader has an invariant cross-section. 22. The power semiconductor package of claim 11 , wherein said gate electrode heat spreader that has a constant cross-sectional area.

Assignees

Inventors

Classifications

  • changes in structures or sizes · CPC title

  • Multiple strap connectors having different structures or shapes · CPC title

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • Encapsulations, e.g. protective coatings · CPC title

  • using a polymer adhesive, e.g. an adhesive based on silicone or epoxy · CPC title

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Frequently asked questions

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What does patent US9570379B2 cover?
In one implementation, a power semiconductor package includes a power transistor having a first power electrode and a gate electrode on its bottom surface, and a second power electrode on its top surface. The first power electrode is configured for attachment to a first partially etched conductive carrier segment and the gate electrode is configured for attachment to a second partially etched c…
Who is the assignee on this patent?
Infineon Technologies Americas Corp
What technology area does this patent fall under?
Primary CPC classification H10W70/481. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 14 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).