Circuit and method for spin-torque MRAM bit line and source line voltage regulation

Patent metadata

Field	Value
Publication number	US-9196342-B2
Application number	US-201514676100-A
Country	US
Kind code	B2
Filing date	Apr 1, 2015
Priority date	Dec 20, 2011
Publication date	Nov 24, 2015
Grant date	Nov 24, 2015

Abstract

Circuitry and a method for regulating voltages applied to magnetoresistive bit cells of a spin-torque magnetoresistive random access memory (ST-MRAM) reduces time-dependent dielectric breakdown stress of the word line transistors. During a read or write operation, only the ends of the selected bit cells are pulled down to a low voltage and/or pulled up to a high voltage depending on the operation (write 0 , write 1 , and read) being performed. The ends of the unselected bit cells are held at a precharge voltage while separately timed signals pull up or pull down the ends of the selected bit cells during read and write operations.

First claim

What is claimed is:

1. A method of operation of a magnetoresistive memory that includes a plurality of magnetic bit cells, each magnetic bit cell of the plurality of magnetic bit cells including a magnetic tunnel junction coupled in series with a select transistor, the method comprising:
pulling a first end of each magnetic bit cell of the plurality of magnetic bit cells to a precharge voltage;
pulling a second end of each magnetic bit cell of the plurality of magnetic bit cells…

Assignees

• Everspin Technologies Inc

Inventors

• Alam Syed M
• Andre Thomas

Classifications

• G11C11/16

  Physics · mapped topic

• G11C11/1693 Primary

  Physics · mapped topic

• G11C11/1653

  Physics · mapped topic

• G11C11/1675 Primary

  Physics · mapped topic

• G11C11/165

  Physics · mapped topic