Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9165628-B2
Application number	US-201514734799-A
Country	US
Kind code	B2
Filing date	Jun 9, 2015
Priority date	Mar 23, 2011
Publication date	Oct 20, 2015
Grant date	Oct 20, 2015

Abstract

A semiconductor memory device includes: a plurality of word lines extending in a first direction; first to third bit lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements each having a first terminal connected to either one of the first and third bit lines; a plurality of active areas extending in a direction oblique to the first direction while intersecting with the first to third bit lines; a plurality of select transistors provided on the active areas and each having a gate connected to a corresponding one of the word lines, and a current path whose one end is connected to a second terminal of a corresponding one of the variable resistance elements; and a plurality of contact plugs each connecting the other end of the current path of a corresponding one of the select transistors to the second bit line, wherein each of the active areas includes two select transistors sharing a diffusion region, the variable resistance elements includes a first variable resistance element group and a second variable resistance element group, the first variable resistance element group including variable resistance elements aligned in the second direction below the first bit line, and each disposed between adjacent two of the word lines, the second variable resistance element group including variable resistance elements aligned in the second direction below the third bit line, and each disposed between adjacent two of the word lines, and the contact plugs are aligned in the second direction below the second bit line, and are each disposed between adjacent two of the word lines.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a first word line;
a first, a second, and a third bit line;
a first select transistor including a gate electrode connected to the first word line, and one end of the first select transistor connected to the first bit line via a first variable resistance element and other end of the first select transistor connected to the second bit line;
a second select transistor including a gate electrode connected to the first word line, and one end of the second select transistor connected to the third bit line via a second variable resistance element and other end of the second select transistor connected to the second bit line; and
a control circuit configured to apply a first voltage to the first word line, to apply a second voltage to the first bit line, to apply a third voltage different from the second voltage to the second bit line, and to set the third bit line in a floating state.

2. The semiconductor memory device according to claim 1 , wherein
the second voltage is higher than the third voltage.

3. The semiconductor memory device according to claim 1 , wherein
the second voltage is lower than the third voltage.

4. The semiconductor memory device according to claim 1 , wherein the control circuit is configured to apply the first voltage to the first bit line after applying the third voltage to the second bit line.

5. The semiconductor memory device according to claim 1 , further comprising:
a fourth, a fifth, and a sixth bit line;
a third select transistor including a gate electrode connected to the first word line, and one end of the third select transistor connected to the fourth bit line via a third variable resistance element and other end of the third select transistor connected to the fifth bit line; and
a fourth select transistor including a gate electrode connected to the first word line, and one end of the fourth select transistor connected to the sixth bit line via a fourth variable resistance element and other end of the fourth select transistor connected to the fifth bit line;
wherein the control circuit is configured to apply a fourth voltage to the fourth bit line and to apply a fifth voltage different from the second voltage to the fifth bit line.

6. The semiconductor memory device according to claim 5 , wherein the fourth voltage is different from the fifth voltage.

7. The semiconductor memory device according to claim 5 , wherein the second voltage is different from the fourth voltage.

8. The semiconductor memory device according to claim 5 , wherein the second voltage is equal to the fourth voltage.

9. The semiconductor memory device according to claim 5 , wherein the control circuit is configured to apply a sixth voltage equal to the third voltage to the sixth bit line.

10. The semiconductor memory device according to claim 5 , wherein the control circuit is configured to set the sixth bit line in floating state.

11. The semiconductor memory device according to claim 5 , wherein the third voltage is equal to the fourth voltage.

Assignees

• Toshiba Kk

Inventors

• Watanabe Toshiharu
• Asao Yoshiaki

Classifications

• G11C11/1655 Primary

  Bit-line or column circuits · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C11/165 Primary

  Auxiliary circuits · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title