Current modulation circuit

Patent metadata

Field	Value
Publication number	US-9568927-B2
Application number	US-201414270677-A
Country	US
Kind code	B2
Filing date	May 6, 2014
Priority date	May 6, 2014
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A modulated digital input signal is passed through a conditioning circuit to generate a first input signal. An error amplifier circuit receives the first input signal and a second input signal, and controls the operation of a MOS transistor to generate an output signal that is current modulated. The output signal is sensed to generate a feedback signal. A switching circuit selectively applies the feedback signal as the second input signal in response to a transition of the modulated digital input signal from a first logic state to a second logic state. The switching circuit alternatively selectively applies a fixed reference signal as the second input signal to the error amplifier in response to a transition of the modulated digital input signal from the second logic state to the first logic state.

First claim

What is claimed is:

1. A circuit, comprising:
a controlled current source configured to generate an output current in response to a difference between a first input signal derived from a modulated digital input signal and a second input signal;
a current sensing circuit configured to sense the output current and generate a feedback signal;
a switching circuit configured to selectively apply one of a fixed reference signal and the feedback signal as the second input signal to the controlled current source;
wherein the switching circuit is configured to apply the feedback signal as the second input signal in response to a transition of the modulated digital input signal from a first logic state to a second logic state; and
wherein the switching circuit is configured to apply the fixed reference signal as the second input signal in response to a transition of the modulated digital input signal from the second logic state to the first logic state.

2. The circuit of claim 1 , wherein the switching circuit further comprises a comparator circuit configured to compare the feedback signal to a reference current and impose a delay in the application of the fixed reference signal following said transition of the modulated digital input signal from the second logic state to the first logic state until a result of the comparison indicates that the feedback signal meets the reference current.

3. The circuit of claim 1 , further comprising a conditioning circuit configured to apply a slope to transitions of the modulated digital input signal between the first logic state and second logic state in generating said first input signal.

4. The circuit of claim 3 , wherein the conditioning circuit comprises a capacitance that is configured to be charged and discharged in response to transitions of the modulated digital input signal between the first logic state and second logic state .

5. The circuit of claim 3 , wherein the conditioning circuit comprises a delay circuit configured to delay said first input signal before application to said controlled current source.

6. The circuit of claim 1 , wherein said switching circuit comprises:
a first switch coupled between a source of the fixed reference signal and an input of the controlled current source that is configured to receive the second input signal; and
a second switch coupled between an output of the current sensing circuit configured to generate the feedback signal and said input of the controlled current source that is configured to receive the second input signal.

7. The circuit of claim 6 , further comprising a logic circuit that receives the first input signal and the feedback signal and is configured to generate control signals for controlling actuation of the first switch in response to said transition of the modulated digital input signal from a first logic state to a second logic state and controlling actuation of the second switch in response to said transition of the modulated digital input signal from the second logic state to the first logic state.

8. The circuit of claim 7 , wherein said logic circuit further comprises:
a comparator circuit configured to compare the feedback signal to a reference current; and
logic configured to delay actuation of the second switch following said transition of the modulated digital input signal from the second logic state to the first logic state until said comparator circuit indicates that the feedback signal has met the reference current.

9. The circuit of claim 7 , further comprising a delay circuit configured to delay said first input signal before application to said controlled current source, but wherein said logic circuit is responsive to said first input signal without delay.

10. The circuit of claim 1 , further comprising a clamping circuit configured to clamp a maximum value of said feedback signal.

11. The circuit of claim 1 , wherein said controlled current source comprises:
an error amplifier having a first input configured to receive said first input signal and a second input configured to receive said second input signal and generate a control signal; and
a MOS transistor having a gate terminal coupled to receive said control signal and a source-drain path configured to generate said output current.

12. The circuit of claim 11 , wherein said error amplifier comprises:
a differential amplifier coupled to receive said first and second input signals;
a differential drive circuit having an input coupled to an output of the differential amplifier and having an output; and
a boosting circuit having an input coupled to receive said control signal and having an output coupled to the input of the differential drive circuit.

13. The circuit of claim 12 , wherein said boosting circuit comprises:
a boost amplifier having first and second inputs and an output coupled to the input of the differential drive circuit;
an additional switching circuit configured to selectively apply an additional fixed reference signal or the control signal as the first input of the boost amplifier; and
a reference generator circuit configured to apply a reference to said second input of the boost amplifier.

14. The circuit of claim 13 :
wherein the additional switching circuit is configured to apply the control signal to the first input of the boost amplifier in response to said transition of the modulated digital input signal from the first logic state to the second logic state; and
wherein the additional switching circuit is configured to apply the additional fixed reference signal to the first input of the boost amplifier in response to said transition of the modulated digital input signal from the second logic state to the first logic state.

15. A method, comprising:
generating an output current in response to a difference between a first input signal derived from a modulated digital input signal and a second input signal;
sensing the output current to generate a feedback signal; and
selectively applying a fixed reference signal or the feedback signal as the second input signal, wherein selectively applying comprises:
applying the feedback signal in response to a transition of the modulated digital input signal from a first logic state to a second logic state; and
applying the fixed reference signal in response to a transition of the modulated digital input signal from the second logic state to the first logic state.

16. The method of claim 15 , further comprising:
comparing the feedback signal to a reference current; and
delaying application of the fixed reference signal following said transition of the modulated digital input signal from the second logic state to the first logic state until the feedback signal meets the reference current.

17. The method of claim 15 , further comprising conditioning said first input signal to include slopes at transitions of the modulated digital input signal between the first logic state and second logic state.

18. The method of claim 17 , further comprising:
delaying said first input signal before a comparison to said second input signal; and
applying the feedback signal in response to transition of the first input signal without application of said delay.

19. The method of claim 15 , further comprising clamping a maximum value of said feedback signal.

20. A circuit, comprising:
an input configured to receive a modulated digital input signal;
a conditioning circuit having an input configured to receive the modulated digital input signal and an output configured to generate a

Assignees

• St Microelectronics Inc
• St Microelectronics Srl

Inventors

• Youssef Tom
• Gasparini Alessandro
• Hu Yamu
• Sahoo Naren K
• Casillan Anthony Junior

Classifications

• G05F1/10

  Regulating voltage or current  (G05F1/02 takes precedence) · CPC title

• G05F1/561 Primary

  Voltage to current converters (amplifiers H03F) · CPC title