Constant current generating circuit using on-chip calibrated resistor and related method thereof

Patent metadata

Field	Value
Publication number	US-9250642-B2
Application number	US-201314086972-A
Country	US
Kind code	B2
Filing date	Nov 22, 2013
Priority date	Nov 23, 2012
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A constant current generating circuit and constant current generating method applied to a chip are provided, where the chip includes a first current generating circuit and a second current generating circuit, the second current generating circuit includes a transistor and an adjustable resistor. The constant current generating method includes: connecting an external resistor to the first current generating circuit to make the first current generating circuit use the external resistor to generate a first current; utilizing the second current generating circuit to generate a second current; adjusting the adjustable resistor in accordance with the first current and the second current to make the second current substantially equal to the first current, where the second current serves as a constant current of the chip.

First claim

What is claimed is:

1. A constant current generating circuit disposed in a chip, comprising:
a first current generating circuit, comprising a first transistor, wherein the first transistor is coupled to a contact of the chip; and in a chip testing phase, the contact is utilized to connect to an external resistor for allowing the first current generating circuit to generate a first current;
a second current generating circuit, comprising a second transistor and an adjustable resistor, the second current generating circuit arranged to generate a second current;
a current mirror;
a switch module, coupled between the first current generating circuit, the second current generating circuit and the current mirror, the switch module arranged to selectively connect the first current generating circuit or the second current generating circuit to the current mirror to make the current mirror duplicate the first current or the second current; and
a calibration circuit, coupled to the current mirror, the calibration circuit arranged to adjust a resistance value of the adjustable resistor in accordance with the first current and the second current duplicated by the current mirror to make the second current substantially equal to the first current, wherein the second current serves as a constant current of the chip;
wherein in the chip testing phase, the switch module connects the first current generating circuit to the current mirror, and disconnects the second current generating circuit from the current mirror, and the calibration circuit receives the first current duplicated by the current mirror; and the switch module further connects the second current generating circuit to the current mirror, and disconnects the first current generating circuit from the current mirror, and the calibration circuit adjusts the resistance value of the adjustable resistor in accordance with the first current and the second current duplicated by the current mirror to make the second current substantially equal to the first current;
wherein the calibration circuit comprises an analog front end circuit of the chip; and the calibration circuit comprises:
a transmitting circuit, arranged for receiving the first current duplicated by the current mirror to generate a first voltage, and receiving the second current duplicated by the current mirror to generate a second voltage;
a receiving circuit, coupled to the transmitting circuit, the receiving circuit arranged for receiving the first voltage to generate a first digital code, and receiving the second voltage to generate a second digital code; and
a digital signal processor, coupled to the receiving circuit, the digital signal processor arranged for adjusting the resistance value of the adjustable resistor in accordance with the first digital codes and the second digital code.

2. The constant current generating circuit of claim 1 , wherein the chip is a network control chip, and the transmitting circuit and the receiving circuit in the network control chip are utilized to send and receive network related signals, respectively.

3. The constant current generating circuit of claim 1 , wherein the digital signal processor comprises a plurality of electronic fuses, and the digital signal processor controls the plurality of electronic fuses to generate a correction code in accordance with the first digital code and the second digital code, and the correction code is used to adjust the resistance value of the adjustable resistor.

4. A constant current generating method applied to a chip, wherein the chip comprises a first current generating circuit and a second current generating circuit, and the second current generating circuit comprises a transistor and an adjustable resistor, the constant current generating method comprising:
connecting an external resistor to the first current generating circuit such that the first current generating circuit uses the external resistor to generate a first current;
utilizing the second current generating circuit to generate a second current; and
adjusting a resistance value of the adjustable resistor in accordance with the first current and the second current to make the second current substantially equal to the first current, wherein the second current serves as a constant current of the chip;
wherein the step of adjusting the resistance value of the adjustable resistor in accordance with the first current and the second current to make the second current substantially equal to the first current comprises:
utilizing a transmitting circuit of an analog front end circuit of the chip to receive the first current to generate the first voltage, and receive the second current to generate the second voltage;
utilizing a receiving circuit of the analog front end circuit of the chip to receive the first voltage to generate the first digital code, and receive the second voltage to generate the second digital code; and
adjusting the resistance value of the adjustable resistor in accordance with the first digital codes and the second digital code;

wherein the chip is a network control chip, and the transmitting circuit and the receiving circuit in the network control chip are utilized to send and receive network related signals, respectively.

5. A constant current generating method applied to a chip, wherein the chip comprises a first current generating circuit and a second current generating circuit, and the second current generating circuit comprises a transistor and an adjustable resistor, the constant current generating method comprising:
connecting an external resistor to the first current generating circuit such that the first current generating circuit uses the external resistor to generate a first current;
utilizing the second current generating circuit to generate a second current; and
adjusting a resistance value of the adjustable resistor in accordance with the first current and the second current to make the second current substantially equal to the first current, wherein the second current serves as a constant current of the chip;
wherein the step of adjusting the resistance value of the adjustable resistor in accordance with the first current and the second current to make the second current substantially equal to the first current comprises:
receiving the first current to generate a first voltage;
receiving the first voltage to generate a first digital code;
receiving the second current to generate a second voltage;
receiving the second voltage to generate a second digital code; and
controlling a plurality of electronic fuses of the chip to generate a correction code in accordance with the first digital code and the second digital code, wherein the correction code is used to adjust the resistance value of the adjustable resistor.

Assignees

• Realtek Semiconductor Corp

Inventors

• Wu Chien-Ming

Classifications

• G05F1/561 Primary

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