Reference current generator with switch capacitor

Patent metadata

Field	Value
Publication number	US-9356509-B2
Application number	US-201313954746-A
Country	US
Kind code	B2
Filing date	Jul 30, 2013
Priority date	Jul 30, 2013
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

Exemplary embodiments are related to current generators. A device may include a first integration path for charging a first integration capacitor during a first phase and a second integration path for charging a second integration capacitor during a second phase. The first integration capacitor may be configured for charging a capacitor coupled to an amplifier during the second phase and the second integration capacitor may be configured for charging the capacitor during the first phase.

First claim

What is claimed is:

1. A device, comprising:
a first integration path for charging a first integration capacitor during a first phase, the first integration capacitor being configured to charge a hold capacitor coupled to an amplifier during a second phase;
a second integration path for charging a second integration capacitor during the second phase, the second integration capacitor being configured to charge the hold capacitor during the first phase;
a switchable element for enabling the first integration capacitor to discharge during the second phase and another switchable element for enabling the second integration capacitor to discharge during the first phase; and
a compensation capacitor having a first element coupled to a supply voltage and a second element coupled to each of an output of the amplifier, a gate of a first transistor of the first integration path, and a gate of a second transistor of the second integration path.

2. The device of claim 1 , the first integration path including a switchable element for coupling the first integration capacitor to a supply voltage during the first phase and the second integration path including another switchable element for coupling the second integration capacitor to the supply voltage during the second phase.

3. The device of claim 1 , each of the first integration path and the second integration path including a transistor for coupling a supply voltage to the respective first and second integration capacitors.

4. The device of claim 1 , further comprising a current mirror including at least one of the first integration path and the second integration path and an output path for generating a reference current.

5. The device of claim 1 , further comprising a tail current source coupled to the amplifier.

6. A device, comprising:
a hold capacitor coupled to an input of an amplifier;
a first integration capacitor configured for selectively charging the hold capacitor;
a second integration capacitor configured for selectively charging the hold capacitor,
wherein the first integration capacitor is selectively configured to receive a charge during a first time period and the second integration capacitor is selectively configured to receive a charge during a second, different time period,
the first integration capacitor is configured for selectively charging the hold capacitor during at least a portion of the second, different time and the second integration capacitor is configured for selectively charging the hold capacitor during at least a portion of the first time period, and
the first integration capacitor is selectively configured to discharge during at least a portion of the second, different time period, and the second integration capacitor is selectively configured to discharge during at least a portion of the first time period;
further comprising:
a first transistor having a gate coupled to an output of the amplifier, a source switchably coupled to a supply voltage, and a drain coupled to the first integration capacitor;
a second transistor having a gate coupled to the output of the amplifier, a source switchably coupled to the supply voltage, and a drain coupled to the second integration capacitor;
a third transistor having a gate coupled to the output of the amplifier, a source switchably coupled to the supply voltage, and a drain configured to convey a reference current; and
a compensation capacitor coupled between the supply voltage and the output of the amplifier.

7. The device of claim 6 , the hold capacitor having one side coupled to a ground voltage and another side coupled to a node, the node further coupled to the input of the amplifier.

8. The device of claim 7 , each of the first integration capacitor and the second integration capacitor configured for selectively coupling to the node.

9. The device of claim 6 , further comprising a tail current source coupled to the amplifier and configured to selectively couple to a ground voltage to generate a tail current during at least a portion of each of the first time period and the second, different time period.

10. A method, comprising:
coupling a first capacitor to a supply voltage during a phase via a first transistor, wherein the supply voltage is coupled to a first element of a compensation capacitor;
coupling a second capacitor to the supply voltage during another, different phase via a second transistor;
coupling the second capacitor to a hold capacitor during at least a portion of the phase, the hold capacitor being coupled to an amplifier;
coupling the first capacitor to the hold capacitor during at least a portion of the another, different phase;
discharging the first capacitor during at least a portion of the another, different phase; and
discharging the second capacitor during at least a portion of the phase,
wherein a second element of the compensation capacitor is coupled to each of an output of the amplifier, a gate of the first transistor, and a gate of the second transistor.

11. The method of claim 10 , further comprising conveying a voltage from the hold capacitor to an input of an amplifier during each of the phase and the another, different phase.

12. The method of claim 11 , further comprising generating a tail current between the amplifier and a ground voltage during at least a portion of the phase and at least a portion of the another, different phase.

13. The method of claim 10 , further comprising:
charging the first capacitor during a complete clock cycle in the phase; and
charging the second capacitor during another complete clock cycle in the another, different phase.

14. A method, comprising:
generating a voltage at an input of an amplifier;
charging a hold capacitor coupled to the input of the amplifier via a first integration capacitor during a portion of a first phase; and
charging the hold capacitor via a second integration capacitor during a portion of a second, different phase;
discharging the first integration capacitor during a portion of the first phase after charging the hold capacitor;
discharging the second integration capacitor during a portion of the second, different phase after charging the hold capacitor;
selectively coupling a supply voltage to the first integration capacitor via a first transistor having a gate coupled to an output of the amplifier, a source switchably coupled to the supply voltage, and a drain coupled to the first integration capacitor, wherein a compensation capacitor is coupled between the supply voltage and the output of the amplifier;
selectively coupling the supply voltage to the second integration capacitor via a second transistor having a gate coupled to the output of the amplifier, a source switchably coupled to the supply voltage, and a drain coupled to the second integration capacitor; and
conveying a reference current via a third transistor having a gate coupled to the output of the amplifier, a source switchably coupled to the supply voltage, and a drain configured to convey the reference current.

15. The method of claim 14 , further comprising:
charging the first integration capacitor during the second, different phase; and
charging the second integration capacitor during the first phase.

16. A device, comprising:
means for generating a voltage at an input of an amplifier;
means for charging a hold capacitor coupled to the input of the amplifier via a first integration capacitor during a portion of a first phase;
means for charging the hold capacitor via a second integration capacitor during a portion of a second, different phase;
means for discharging the first i

Assignees

• Qualcomm Inc

Inventors

• Hinrichs Jeffrey Mark

Classifications

• G05F1/561 Primary

  Voltage to current converters (amplifiers H03F) · CPC title

• G05F1/575

  characterised by the feedback circuit · CPC title

• H02M3/156 Primary

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title