Formation of DRAM capacitor among metal interconnect

Patent metadata

Field	Value
Publication number	US-9565766-B2
Application number	US-201113976085-A
Country	US
Kind code	B2
Filing date	Oct 7, 2011
Priority date	Oct 7, 2011
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

Techniques are disclosed for integrating capacitors among the metal interconnect for embedded DRAM applications. In some embodiments, the technique uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation. This interconnect metal removal precludes that metal from contaminating the hi-k dielectric of the capacitor. Another benefit is increased height (surface area) of the capacitor, which allows for increased charge storage. In one example embodiment, an integrated circuit device is provided that includes a substrate having at least a portion of a DRAM bit cell circuitry, an interconnect layer on the substrate and including one or more metal-containing interconnect features, and a capacitor at least partly in the interconnect layer and occupying space from which a metal-containing interconnect feature was removed. The integrated circuit device can be, for example, a processor or a communications device.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
a substrate having at least a portion of a dynamic random access memory (DRAM) bit cell circuitry;
an interconnect layer on the substrate defining a plurality of interconnect feature spaces, each interconnect feature space of the plurality of interconnect feature spaces having a cross-sectional scale and cross-sectional shape that includes sidewalls and a bottom that is closer to the substrate than the sidewalls;
one or more metal-containing interconnect features, each occupying a corresponding interconnect feature space of a first set of interconnect feature spaces of the plurality of interconnect feature spaces; and
one or more capacitor features, each occupying a corresponding interconnect feature space of a second set of interconnect features spaces of the plurality of interconnect feature spaces, each of which also has the cross-sectional scale and the cross-sectional shape, each capacitor feature comprising:
a bottom electrode, a dielectric, and a top electrode; and
a diffusion barrier layer conforming to each of the interconnect feature spaces having the cross-sectional shape.

2. The device of claim 1 wherein the diffusion barrier layer comprises tantalum.

3. The device of claim 1 wherein the interconnect layer is one of many in a stack of interconnect layers, and one or more metal-containing interconnect features of one of the interconnect layers electrically connect that layer to other interconnect layers in the stack.

4. The device of claim 3 wherein each of the lower electrode, dielectric, and upper electrode of the capacitor feature is at least partly in two or more consecutive layers of the stack.

5. The device of claim 4 wherein the second space is at least partly in the bottom of the two or more consecutive layers of the stack.

6. The device of claim 1 wherein the interconnect layer further includes a dielectric material in which the one or more metal-containing interconnect features reside.

7. The device of claim 1 wherein the capacitor feature is configured as a metal-insulator-metal (MIM) capacitor.

8. The device of claim 1 wherein the bottom electrode is electrically coupled to a transistor of the DRAM bit cell circuitry.

9. The device of claim 1 wherein the dielectric comprises a high-k dielectric having a dielectric constant greater than that of silicon dioxide.

10. The device of claim 1 wherein the bottom electrode is electrically coupled to a transistor of the DRAM bit cell circuitry, the DRAM bit cell circuitry comprising a plurality of DRAM bit cells, each cell having an access transistor and a capacitor at least partly occupying space of the interconnect layer.

11. The device of claim 1 wherein at least one of the metal-containing interconnect features comprise a metal landing pad, a metal line, a via, or a combination thereof.

12. The device of claim 1 wherein the device is a processor, a communications device, or a computing device.

13. A system, comprising:
a processor integrated circuit comprising the device of claim 1 ; and
at least one of a communications integrated circuit and a display.

14. The integrated circuit device of claim 1 , wherein the cross-sectional shape is a dual damascene shape that includes a first width corresponding to a metal line and an adjacent second width less than the first width corresponding to a via.

15. The integrated circuit device of claim 1 , wherein the cross-sectional shape includes:
a tapered portion having a uniformly decreasing width; and
a dual damascene shaped structure having a first width corresponding to a metal line and an adjacent second width less than the first width corresponding to a via; and
wherein the tapered portion tapers down to the dual damascene shaped structure.

16. The integrated circuit device of claim 1 , wherein the cross-sectional shape has an aspect ratio of from 5:1 to 10:1.

17. An integrated circuit device, comprising:
a substrate having at least a portion of a dynamic random access memory (DRAM) bit cell circuitry;
an interconnect layer on the substrate defining a plurality of interconnect feature spaces, each interconnect feature space of the plurality of interconnect feature spaces having a cross-sectional scale and cross-sectional shape that includes sidewalls and a bottom that is closer to the substrate than the sidewalls;
one or more metal-containing interconnect features, each occupying a corresponding interconnect feature space of a first set of interconnect feature spaces of the plurality of interconnect feature spaces, wherein each metal-containing interconnect feature is separated from insulator material of the interconnect layer by a diffusion barrier conforms to each of the interconnect feature spaces of the plurality of interconnect feature spaces defined by the interconnect layer; and
one or more capacitors, each occupying a corresponding interconnect feature space of a second set of interconnect features spaces of the plurality, each of which also has the cross-sectional scale and cross-sectional shape, each capacitor comprising:
a bottom electrode, a dielectric, and a top electrode wherein the bottom electrode is also separated from the insulator material of the interconnect layer by the diffusion barrier of the interconnect layer conforming to each of the interconnect features spaces of the plurality of interconnect feature spaces defined by the interconnect layer.

18. The device of claim 17 wherein the interconnect layer is one of many in a stack of interconnect layers, and one or more metal-containing interconnect features of one of the interconnect layers electrically connect that layer to other layers in the stack, and the capacitor is at least partly in two or more consecutive layers of the stack.

19. The device of claim 17 wherein the bottom electrode is electrically coupled to a transistor of the DRAM bit cell circuitry, and the device is a processor or communications device.

20. The integrated circuit device of claim 17 , wherein the cross-sectional shape of each interconnect feature space of the plurality of interconnect features spaces comprises a dual damascene shaped structure that includes a first width corresponding to a metal line and an adjacent second width less than the first width corresponding to a via.

21. The integrated circuit device of claim 20 , wherein the cross-sectional shape of the one or more capacitors further includes:
a tapered portion having a width that decreases from a top of the tapered portion to a bottom of the tapered portion,
wherein the tapered portion tapers down to the dual damascene shaped structure.

22. An integrated circuit device, comprising:
a substrate having at least a portion of a dynamic random access memory (DRAM) bit cell circuitry including a transistor;
an interconnect layer on the substrate defining a plurality of interconnect pathways, each interconnect pathway of the plurality of interconnect pathways having a cross-sectional scale and cross-sectional shape that includes sidewalls and a bottom that is closer to the substrate than the sidewalls;
one or more metal-containing interconnect features, each occupying an interconnect pathway of a first set of interconnect pathways of the plurality of interconnect pathways; and
one or more capacitors, each occupying a corresponding interconnect pathway of a second set of interconnect pathways of the plurality of interconnect pathways, each capacitor comprising:
a b

Assignees

• Lindert Nick
• Steigerwald Joseph M
• Singh Kanwal Jit
• Intel Corp

Inventors

• Lindert Nick
• Steigerwald Joseph M
• Singh Kanwal Jit

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H01L28/90

  Electricity · mapped topic

• H01L28/87

  Electricity · mapped topic

• H01L23/5223

  Electricity · mapped topic