Method of forming semiconductor device

Patent metadata

Field	Value
Publication number	US-9564520-B1
Application number	US-201615199684-A
Country	US
Kind code	B1
Filing date	Jun 30, 2016
Priority date	Jun 30, 2016
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A method of forming a semiconductor device is disclosed. A sacrificial oxide layer is formed on a substrate having first and second areas. Using a photoresist mask exposing the first area and covering the second area as a mask layer, by a wet etching process, the sacrificial oxide layer in the first area and an edge portion of the sacrificial oxide layer in the second area are simultaneously removed, wherein the sacrificial oxide layer remained in the second area has a sidewall with a slope smaller than 40 degrees. An oxide-nitride-oxide (ONO) layer is formed over the first and second areas. The sacrificial oxide layer and the ONO layer formed thereon in the second area are removed, so that the ONO layer remained in the first area forms a first gate insulating layer in the first area. A second gate insulating layer is formed in the second area.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
providing a substrate having a first area and a second area;
forming a sacrificial oxide layer on the substrate in the first and second areas;
forming a photoresist mask on the sacrificial oxide layer to expose the first area and cover the second area;
using the photoresist mask as a mask layer, by a wet etching process, simultaneously removing the sacrificial oxide layer in the first area and an edge portion of the sacrificial oxide layer in the second area covered by the photoresist mask, wherein the sacrificial oxide layer remained in the second area has a sidewall with a slope smaller than 40 degrees;
forming an oxide-nitride-oxide (ONO) layer over the substrate in the first and second areas;
removing the sacrificial oxide layer and the ONO layer formed thereon in the second area, so that the ONO layer remained in the first area forms a first gate insulating layer on the substrate in the first area; and
forming a second gate insulating layer on the substrate in the second area.

2. The method of claim 1 , wherein the edge portion of the sacrificial oxide layer in the second area removed by the wet etching process is disposed adjacent to a boundary of the first and second areas.

3. The method of claim 1 , wherein the step of removing the sacrificial oxide layer in the first area and the edge portion of the sacrificial oxide layer in the second area further comprises using a dry etching process.

4. The method of claim 1 , wherein the sacrificial oxide layer and the ONO layer formed thereon in the second area are simultaneously removed.

5. The method of claim 1 , further comprising forming first and second gates respectively on the first and second gate insulating layers.

6. The method of claim 5 , further comprising performing an implantation process on the substrate by using the first and second gates as a mask.

7. The method of claim 5 , further comprising forming first and second spacers respectively on sidewalls of the first and second gates.

8. The method of claim 7 , further comprising performing an implantation process on the substrate by using the first and second gates and the first and second spacers as a mask.

9. The method of claim 1 , wherein the wet etching process is performed by using a buffered oxide etchant (BOE), and the buffered oxide etchant (BOE) is a solution of HF/NH 4 F in a ratio of 20:1 to 100:1 mixed with water.

10. The method of claim 1 , wherein the wet etching process is performed for about 35 to 45 seconds.

11. The method of claim 1 , wherein a thickness of the sacrificial oxide layer remained in the second area after performing the wet etching process is about 20 to 200 angstroms.

12. The method of claim 1 , wherein the second gate insulating layer comprises an oxide layer.

13. The method of claim 1 , wherein the sidewall of the sacrificial oxide layer remained in the second area has a smooth surface.

14. The method of claim 1 , wherein the first area is a control gate area and the second area is a select gate area.

Assignees

• United Microelectronics Corp

Inventors

• Chen Tzu-Ping

Classifications

• H10P76/403 Primary

  for lift-off processes · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H01L21/31111

  Electricity · mapped topic

• H01L29/66833 Primary

  Electricity · mapped topic